Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs

  • Thomas Hollstein
  • Ralf Ludewig
  • Heiko Zimmer
  • Christoph Mager
  • Simon Hohenstern
  • Manfred Glesner
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

This paper presents a new generic system architecture and design methodology for the design, debugging and testing of complex systems-on-chip (SoC). Starting from a hierarchical generic system architecture, platforms for dedicated application scenarios will be customized. In order to be able to handle very complex submicron designs, the system is based on a globally asynchronous and locally synchronous (GALS) concept. The problem of the increasing functionality versus outer access capabilities ratio is faced by novel embedded and combined debugging and test structures. The integration of debugging possibilities is essential for an efficient co-design of SoC integrated hardware and software, especially for systems with integrated reconfigurable hardware parts.

Keywords

Networks-on-Chip Silicon Debug Built-in Self Test 

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Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Thomas Hollstein
    • 1
  • Ralf Ludewig
    • 1
  • Heiko Zimmer
    • 1
  • Christoph Mager
    • 1
  • Simon Hohenstern
    • 1
  • Manfred Glesner
    • 1
  1. 1.Institute of Microelectronic SystemsDarmstadt University of TechnologyDarmstadtGermany

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