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Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths

  • Eduardo A. C. da Costa
  • Jose C. Monteiro
  • Sergio Bampi
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

This paper addresses the use of low power techniques applied to FIR filter and FFT dedicated datapath architectures. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2’s complement is the most common encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. This architecture uses radix-2m encoding, which leads to a reduction of the number of partial lines. Each group of m bits uses the Gray code, thus potentially further reducing the switching activity both internally and at the inputs. The multiplier architecture is applied to the DSP architectures and compared with the state of the art. Due to the characteristics of the FIR filter and FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations in order to minimize the power consumption in the implemented architectures is also investigated. As will be shown, the use of the low power operators with an appropriate choice of coefficients can contribute for the reduction of power consumption of the FIR and FFT architectures. Additionally, a new algorithm for the partitioning and ordering of the coefficients is presented. This technique is experimented in a Semi-Parallel architecture which enables speedup transformation techniques.

Key words

Hybrid encoding DSP architectures power consumption 

7. References

  1. 1.
    M. Mehendale, S. Sherlekar, and G. Venkatesh, G., Low-Power Realization of FIR Filters on Programmable DSP’s. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):546–553, (1998).CrossRefGoogle Scholar
  2. 2.
    A. Erdogan, and T. Arslan, High Throughput FIR Filter Design for Low Power SOC Applications. In 13 th Annual IEEE International ASIC/SOC Conference, pp. 21–24, (2000).Google Scholar
  3. 3.
    M. Baas, A Low-Power, High-Performance, 1024-Point FFT Processor. IEEE Journal of Solid-State Circuits, 34(3):380–387, (1999).CrossRefGoogle Scholar
  4. 4.
    K. Parhi, Algorithms and Architectures for High-Speed and Low-Power Digital Signal Processing. In Proceedings of 4 th International Conference on Advances in Communications and Control, (1993).Google Scholar
  5. 5.
    E. Mussol, and J. Cortadella, Low-Power Array Multipliers with Transition-Retaining Barriers. PATMOS, pp. 227–235. 2002.Google Scholar
  6. 6.
    E. da Costa, J. Monteiro, and S. Bampi, A New Architecture for 2’s Complement Gray Encoded Array Multiplier. In Proceedings of the XV Symposium on Integrated Circuits and Systems Design, pp. 14–19, (2002).Google Scholar
  7. 7.
    M. Mehendale, S. Sherlekar, and G. Venkatesh, Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. In Eleventh International Conference on VLSI Design, pp. 12–17, (1998).Google Scholar
  8. 8.
    A. Genderen, SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage Waveforms. In Proceedings of the International Conference on Very Large Scale Integration, pp. 79–88, (1989).Google Scholar
  9. 9.
    A. Oppenheim, and R. Schafer, Discrete-Time Signal Processing. London: Prentice Hall Signal International, (1989).MATHGoogle Scholar
  10. 10.
    P. Kumhom, J. Johnson, and P. Nagvajara, Design and Implementation of a Universal FFT Processor. In 13 th Annual IEEE International ASIC/SOC Conference, pp. 182–186, (2000).Google Scholar
  11. 11.
    S. He, and M. Torkelson, Design and Implementation of a 1024-point Pipeline FFT Processor. In IEEE CICC, pp. 131.134, (1998).Google Scholar
  12. 12.
    S. Douglas, and et al., 1998, A Pipelined LMS Adaptive FIR Filter Architecture without Adaption Delay. IEEE Transactions on Signal Processing, 46(3), (1998).Google Scholar
  13. 13.
    S. Yu, and E. Swartzlander, A New Pipelined Implementation of the Fast Fourier Transform. In Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, pp. 423–427, (2000).Google Scholar
  14. 14.
    K. Muhammad, R. Staszewski, and P. Balsara, Speed, Power, Area, and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read Channels. IEEE Transactions on VLSI Systems, 9(1):42–51, (2001).CrossRefGoogle Scholar
  15. 15.
    M. Mehendale, S. Sherlekar, and G. Venkatesh, Techniques for Low Power Realization of FIR Filters. In Design Automation Conference, pp. 404–416, (1995).Google Scholar
  16. 16.
    A. Chandrakasan, and R. Brodersen, Low Power Digital CMOS Design. Kluwer Academic Publishers, (1995).Google Scholar
  17. 17.
    M. Stan, and W. Burleson, Low-Power Encodings for Global Communication in CMOS VLSI. IEEE Trans. on VLSI Systems, (1997).Google Scholar
  18. 18.
    M. Stan, and W. Burleson, Limited-Weight Codes for Low-Power I/O. IEEE International Workshop on Low Power Design, (1997).Google Scholar
  19. 19.
    M. Stan, and W. Burleson, Bus-Invert Coding for Low-Power I/O. IEEE Transactions on VLSI Systems, (1995).Google Scholar
  20. 20.
    P. Ramos, and A. Oliveira, Low Overhead Encodings for Reduced Activity in Data and Address Buses. In IEEE International Symposium on Signals, Circuits and Systems, pp. 21–24, (1999).Google Scholar
  21. 21.
    I. Khater, A. Bellaouar, and M. Elmasry, Circuit Techniques for CMOS Low-Power High-Performance Multipliers. IEEE Journal of Solid-State Circuits, 31:1535–1546, (1996).CrossRefGoogle Scholar
  22. 22.
    E. Sentovich, and et al., SIS: A System for Sequential Circuit Synthesis, Technical report, (1992).Google Scholar

Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Eduardo A. C. da Costa
    • 1
  • Jose C. Monteiro
    • 2
  • Sergio Bampi
    • 3
  1. 1.Universidade Católica dePelotas (UCPel)PelotasRS-Brazil
  2. 2.Instituto de Engenharia e Sistemas de Computadores (INESC-ID)LisboaPortugal
  3. 3.Universidade Federal do Rio Grande do Sul (UFRGS)Porto AlegreRS-Brazil

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