Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes

  • Stephan Henzler
  • Philip Teichmann
  • Markus Koban
  • Jörg Berthold
  • Georg Georgakos
  • Doris Schmitt-Landsiedel
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

Two different schemes to switch-off unused circuit blocks (ZigZag-cut-off scheme1 and n-/p-block MTCMOS cut-off scheme2,3,4,5,6 are examined in deep-submicron technologies by analytical investigation and simulation. The theoretical basis of the ZigZag-scheme is given and particular design constraints are discussed. It is shown that the power-saving benefits of the ZigZag-scheme are critically dependent on the gate-leakage, whereas n- or p-block switching keep their effectiveness. Finally it is derived that n-block switching tends to cause severe glitch activity during power-up process degrading both power-up-time and energy loss. The ZigZag-scheme however does not suffer from this effect. The advantages and drawbacks of the two schemes are compared depending on the available technology generation. Finally recent extensions to ZigZag are discussed.

Key words

MTCMOS ZigZag ZZSCCMOS Circuit Block Switch-Off Sleep-Transistor Scheme Gate-Tunneling GSCMOS 

References

  1. 1.
    K-S. Min, H. Kawaguchi, T. Sakurai et al., Zigzag Super Cut-off CMOS Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era, ISSCC 2003 Google Scholar
  2. 2.
    R.K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, S. Borkar et al., High-performance, Low-power, and Leakage-tolerance Challenges for Sub-70nm Microprocessor Circuits”, ESSCIRC (2002)Google Scholar
  3. 3.
    S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, JSSC, 30(8) (1995)Google Scholar
  4. 4.
    B. Calhoun, F. Honoré, A. Chandrakasan, A Leakage Reduction Methodology for Distributed MTCMOS, JSSC 39(5) (2004)Google Scholar
  5. 5.
    J. Tschanz, S. Narendra et al., Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors, JSSC 38(11) 1838–1845 (2003)Google Scholar
  6. 6.
    H. Kawaguchi, K. Nose, T. Sakurai, A Super Cut-Off (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current, JSSC 35(10) 1498–1501 (2000)Google Scholar
  7. 7.
    S.I.A., ITRS, International Technology Roadmap for Semiconductors, 2002Google Scholar
  8. 8.
    J. Kao, A. Chandrakasan, D. Antoniadis, Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology, DAC (1997)Google Scholar
  9. 9.
    St. Henzler, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel, Two Level Compact Simulation Methodology For Timing Analysis Of Power-Switched Circuits, PATMOS 789–798, (2004).Google Scholar
  10. 10.
    W-C. Lee, C. Hu et al., Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction-and Valence-Band Electron and Hole Tunneling, IEEE Transactions on Electron Devices, 48(7), (2001)Google Scholar
  11. 11.
    J.W. Fattaruso, Buss et al., Current Trends in analog Design, Short Course on System-on-a-Chip, ISSCC 2003 Google Scholar
  12. 12.
    M. Drazdziulis, P. Larsson-Edefors et al., A Power Cut-Off Technique for Gate Leakage Suppression, ESSCIRC (2004)Google Scholar
  13. 13.
    St. Henzler, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel, A Fast Power-Efficient Circuit-Block Switch-Off Scheme, IEE Electronics Letters, 40(2) 103–104, (2004)CrossRefGoogle Scholar

Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Stephan Henzler
    • 1
  • Philip Teichmann
    • 1
  • Markus Koban
    • 1
  • Jörg Berthold
    • 2
  • Georg Georgakos
    • 2
  • Doris Schmitt-Landsiedel
    • 1
  1. 1.Technical University of MunichMunich
  2. 2.Infineon TechnologiesGermany

Personalised recommendations