Optimizing SOC Test Resources Using Dual Sequences

  • Wei Zou
  • Chris C. N. Chu
  • Sudhakar M. Reddy
  • Irith Pomeranz
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of the proposed method.

References

  1. 1.
    E. J. Marinissen, S. K. Goel and M. Lousberg, Wrapper Design for Embedded Core test, pp.911–920, ITC, 2000.Google Scholar
  2. 2.
    P. Varma and S. Bhatia, A Structured Test Re-Use Methodology for Core-Based System Chips, pp. 294–302, ITC, 1998.Google Scholar
  3. 3.
    E. J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores, pp. 284–293, ITC, 1998.Google Scholar
  4. 4.
    P. T. Gonciari, B. M. Al-Hashimi and N. Nicolici, Addressing Useless Memory in Core-Based System-on-a-Chip Test, pp. 423–430, VTS, 2002.Google Scholar
  5. 5.
    E. J. Marinissen, R. Kapur, and Y. Zorian, On Using IEEE P1500 SECT for Test Plug-n-Play, pp. 770–777, ITC, 2000.Google Scholar
  6. 6.
    W. Zou, S. M. Reddy, I. Pomeranz and Y. Huang, SOC Test Scheduling Using Simulated Annealing, pp. 325–330 VTS, 2003.Google Scholar
  7. 7.
    E. Larsson and Z. Peng, An Integrated System-On-Chip Test Framework, pp. 138–144, DATE, 2001.Google Scholar
  8. 8.
    E. Larsson, Z. Peng and G. Carlsson, The Design and Optimization of SOC Test Solutions, pp. 523–530, ICCAD, 2001.Google Scholar
  9. 9.
    K. Chakrabarty, Design of System-on-Chip Test Access Architectures using Integer Linear Programming, pp. 127–134, VTS, 2000.Google Scholar
  10. 10.
    Y. Huang et. al., Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design, pp. 265–270, ATS, 2001.Google Scholar
  11. 11.
    V. Iyenger, K. Chakrabarty and E. J. Marinssen, Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip, pp. 1023–1032, ITC, 2001.Google Scholar
  12. 12.
    V. Iyenger, K. Chakrabarty and E. J. Marinssen, On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization, pp. 253–258, VTS, 2002.Google Scholar
  13. 13.
    V. Iyengar and K. Chakrabarty and E. J. Marinssen, Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume reduction for SOCs, pp. 685–690, DAC, 2002.Google Scholar
  14. 14.
    Y. Huang et al., Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on3-D Bin Packing Algorithm, pp. 74–82, ITC, 2002.Google Scholar
  15. 15.
    S. K. Goel and E. J. Marinissen, Effective and Efficient Test Architecture Design for SOCs, pp. 529–538, ITC, 2002.Google Scholar
  16. 16.
    S. Koranne and V. Iyengar, On the Use of k-tuples for SoC Test Schedule Representation, pp. 539–548, ITC, 2002.Google Scholar
  17. 17.
    S. Kirkpatrick et al., Optimization by Simulated Annealing, pp.671–680, Science, Vol.220, No.4598, 1983.MathSciNetGoogle Scholar
  18. 18.
    E. J. Marinissen, V. Iyengar and K. Chakrabarty. ITC2002 SOC Benchmarking initiative, http://www.extra.research.philips.com/itc02socbenchm.Google Scholar
  19. 19.
    H. Murata, et. al., VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair, pp. 1518–1524, IEEE, TCAD, 1996.Google Scholar
  20. 20.
    V. Iyengar et. al., Test resource Optimization for multi-Site testing of SOCs under ATE memory Depth constrains, pp. 1159–1168, ITC, 2002.Google Scholar
  21. 21.
    P. T. Gonciari and B. M. Al-Hashimi, Useless Memory Allocation in System-on-Chip test: Problems and Solutions, pp. 423–429, VTS, 2002.Google Scholar
  22. 22.
    J. Bedsole, R. Raina, A. Crouch and M. S. Abadir, Very Low Cost Tester: Opportunities and Challenges, pp.738–747, ITC, 2001.Google Scholar

Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Wei Zou
    • 1
  • Chris C. N. Chu
    • 2
  • Sudhakar M. Reddy
    • 1
  • Irith Pomeranz
    • 3
  1. 1.Electrical & Computer EngineeringUniversity of IowaIowa CityUSA
  2. 2.Electrical & Computer EngineeringIowa State UniversityAmesUSA
  3. 3.Electrical & Computer EngineeringPurdue UniversityWest LafayetteUSA

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