Optimizing SOC Test Resources Using Dual Sequences

  • Wei Zou
  • Chris C. N. Chu
  • Sudhakar M. Reddy
  • Irith Pomeranz
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)


In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of the proposed method.


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Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Wei Zou
    • 1
  • Chris C. N. Chu
    • 2
  • Sudhakar M. Reddy
    • 1
  • Irith Pomeranz
    • 3
  1. 1.Electrical & Computer EngineeringUniversity of IowaIowa CityUSA
  2. 2.Electrical & Computer EngineeringIowa State UniversityAmesUSA
  3. 3.Electrical & Computer EngineeringPurdue UniversityWest LafayetteUSA

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