Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures

  • Alexandre M. Amory
  • Leandro A. Oliveira
  • Fernando G. Moraes
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)


With the advance in hardware integration, system-on-a-chip (SoC) test activities using only automatic test equipments (ATEs) result in an expensive option. Hardware-based test may reduce the ATE dependency. However, hardware-based test imposes some constraints like area overhead and processing speed degradation. The main objective of this work is to investigate and evaluate a less intrusive test approach called software-based test. Software-based test uses an embedded processor as source and sink of the test, sending the test patterns and reading the responses. A new integrated design and test environment has been developed to automatically synthesize test programs to test non-programmable cores of SoCs. Some benchmarks ISCAS85 and ISCAS89 are used to evaluate the proposed methodology.

Key words

SoC test Software-based test computer aided test (CAT) LFSR reseeding 

7. References

  1. 1.
    L. Chen, and S. Dey, Software-Based Self-Testing Methodology for Processor Cores. IEEE Transactions on Computer-AidedDesigns. 20(3), 369–380 (2001).CrossRefGoogle Scholar
  2. 2.
    J.-R. Huang, M. K. Iyer, and K.-T. Cheng, A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. In: VLSI Test Symposium. 198–203 (2001).Google Scholar
  3. 3.
    S. Hwang, and J. A. Abraham, Reuse of Addressable System Bus for SOC Testing. In: ASIC/SOC Conference. 215–219 (2001).Google Scholar
  4. 4.
    W. C. Lai, and K. T. Cheng, Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. In: Design Automation Conference. 59–64 (2001).Google Scholar
  5. 5.
    A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, and S. Dey, Embedded Software-Based Self-Test for Programmable Core-Based Designs. IEEE Design and Test of Computers. 19(4), 18–27 (2002).CrossRefGoogle Scholar
  6. 6.
    S. M. Thatte, and J. A. Abraham, A Methodology for Functional Level Testing of Microprocessors. In: International Symposium on Fault-Tolerant Computing. 90–95 (1978).Google Scholar
  7. 7.
    N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, and Y. Zorian, Low-Cost Software-Based Self-Test of RISC Processor Cores. In: Design, Automation and Test in Europe Conference. 164–168 (2003).Google Scholar
  8. 8.
    A. J. Van de Goor, Using March Tests to Test SRAMs. IEEE Design and Test of Computers. 10(1), 8–14 (1993).CrossRefGoogle Scholar
  9. 9.
    Y. Zorian, and A. Ivanov, An Effective BIST Scheme for ROM’s. IEEE Transaction on Computers. 41(5), 646–653 (1992).CrossRefGoogle Scholar
  10. 10.
    S. Hellebrand, H. J. Wunderlich, and A. Hertwig, Mixed-Mode BIST Using Embedded Processors. In: International Test Conference. 195–204 (1996).Google Scholar
  11. 11.
    J. Rajski, and J. Tyszer, Arithmetic Built-in Self-Test for Embedded Systems (Prentice Hall, Upper Saddle River, 1998).Google Scholar
  12. 12.
    Altera Inc. Nios Embedded Processor: 32 bits Programmer’s Reference Manual. (version 2. 1, 2002, 124 p).Google Scholar
  13. 13.
    C. V. Krishna, and N. A. Touba, Reducing Test Data Volume Using LFSR Reseeding with Seed Compression. In: International Test Conference. 321–330 (2002).Google Scholar
  14. 14.
    A. M. Amory, E. Cota, M. S. Lubaszewski, and F. G. Moraes, Reducing Test Time with Processor Reuse in Network-on-Chip Based Systems. In: Symposium on Integrated Circuits and System. 111–116 (2004).Google Scholar

Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Alexandre M. Amory
    • 1
  • Leandro A. Oliveira
    • 1
  • Fernando G. Moraes
    • 2
  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do Sul (UFRGS)Porto AlegreBrazil
  2. 2.Faculdade de InformáticaPontificia Universidade Católica do Rio Grande do Sul (PUCRS)Porto AlegreBrazil

Personalised recommendations