Effect of Power Optimizations on Soft Error Rate

  • Vijay Degalahal
  • R. Ramanarayanan
  • Narayanan Vijaykrishnan
  • Y. Xie
  • M. J. Irwin
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)


Due to technology scaling, devices are getting smaller, faster and operating at lower voltages. The reduced nodal capacitances and supply voltages coupled with more dense and larger chips are increasing soft errors and making them an important design constraint. As designers aggressively address the excessive power consumption problem that is considered as a major design limiter they need to be aware of the impact of the power optimizations on the soft error rates(SER). In this chapter, we analyze the effect of increasing threshold voltage and reducing the operating voltages, widely used for reducing power consumption, on the soft error rate. While reducing the operating voltage increases the susceptibility to soft errors, increasing the threshold voltages offers mixed results. We find that increasing threshold voltage (V t) improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that, in certain circuits, clever use of high V t can improve the robustness to soft errors.


Low Power VLSI Power Optimizations Soft Errors Single Event Upset Reliability Noise Immunity 


  1. [1]
    Berkeley predictive model. Scholar
  2. [2]
    L. Anghel, D. Alexandrescu, and M. Nicolaidis. Evaluation of a soft error tolerance technique based on time and/or space redundancy. In Proceedings of the 13th symposium on Integrated circuits and systems design, page 237. IEEE Computer Society, 2000.Google Scholar
  3. [3]
    Avant! Hspice User Manual, 2003 edition.Google Scholar
  4. [4]
    N. Azizi, A. Moshovos, and F. N. Najm. Low-leakage asymmetric-cell sram. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design, pages 48–51, 2002.Google Scholar
  5. [5]
    R. Baumann. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction. In Digest. International Electron Devices Meeting, 2002. IEDM’ 02, pages 329–332, 2002.Google Scholar
  6. [6]
    R. C. Baumann. Soft errors in advanced semiconductor devices-part i: the three radiation sources. IEEE Transactions on Device and Materials Reliability, 1(1): 17–22, 2001.CrossRefGoogle Scholar
  7. [7]
    M. Baze and S.P. Buchner. Attenuation of single event induced pulses in cmos combinational logic. Nuclear Science, IEEE Transactions on, 44(1):2217–2223, December 1997.CrossRefGoogle Scholar
  8. [8]
    S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23–29, 1999.CrossRefGoogle Scholar
  9. [9]
    S. Borkar, T. Karnik, and V. De. Design and reliability challenges in nanometer technologies. In Proceedings of the 41st annual conference on Design automation, pages 75–75, 2004.Google Scholar
  10. [10]
    S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger. Comparison of error rates in combinational and sequential logic. Nuclear Science, IEEE Transactions on, 44(l):2209–2216, December 1997.CrossRefGoogle Scholar
  11. [11]
    J. Y. Chen. CMOS Devices and Technology for VLSI. Prentice-Hall, Englewood Cliffs, NJ, 1990.Google Scholar
  12. [12]
    V. Degalahal, N. Vijaykrishnan, and M. J. Irwin. Analyzing soft errors in leakage optimized sram designs. In 6th International Conference on VLSI Design, Jan. 2003.Google Scholar
  13. [13]
    K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leakage power. In Proceedings of the 29th annual international symposium on Computer architecture (ISCA-29), pages 148–157, 2002.Google Scholar
  14. [14]
    S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta, and C. Dai. Impact of cmos process scaling and soi on the soft error rates of logic processes. In Digest of Technical Papers. 2001 Symposium on VLSI Technology, pages 73–74, 2001.Google Scholar
  15. [15]
    P. Hazucha and C. Svensson. Impact of cmos technology scaling on the atmospheric neutron soft error rate. IEEE Transactions on Nuclear Science, 47(6), 2000.Google Scholar
  16. [16]
    K. Johansson, P. Dyreklev, O. Granbom, M. C. Calver, S. Fourtine, and. Feuillatre. Inflight and ground testing of single event upset sensitivity in static rams. Nuclear Science, IEEE Transactions on, 45(3): 1628–1632, June 1998.CrossRefGoogle Scholar
  17. [17]
    T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar. Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18u. In Digest of Technical Papers. 2001 Symposium on VLSI Circuits, pages 61–62, 2001.Google Scholar
  18. [18]
    T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla, and S. Borkar. Selective node engineering for chip-level soft error rate improvement [in cmos]. In VLSI Circuits Digest of Technical Papers, 2002. Symposium on, pages 204–205, 2002.Google Scholar
  19. [19]
    S. H. Kulkarni and D. Sylvester. High performance level conversion for dual v/sub dd/ design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 12(9):926–936, September 2004.CrossRefGoogle Scholar
  20. [20]
    L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Soft error and energy consumption interactions: a data cache perspective. In Proceedings of the 2004 international symposium on Low power electronics and design, pages 132–137, 2004.Google Scholar
  21. [21]
    R. Rajaraman, N. Vijaykrishnan, Y. Xie, M. J. Irwin, and K. Bernstein. Soft errors in adder circuits. In MAPLD, 2004.Google Scholar
  22. [22]
    R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J. Irwin, and D. Duarte. Analysis of soft error rate in flip-flops and scannable latches. In SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip], pages 231–234, September 2003.Google Scholar
  23. [23]
    J. Ray, J. C. Hoe, and B. Falsafi. Dual use of superscalar datapath for transient-fault detection and recovery. In Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 214–224. IEEE Computer Society, 2001.Google Scholar
  24. [24]
    E. Rotenberg. Ar-smt: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, page 84. IEEE Computer Society, 1999.Google Scholar
  25. [25]
    K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits. Proceedings of the IEEE, 91(2):305–327, Feb 2003.CrossRefGoogle Scholar
  26. [26]
    N. Seifert, D. Moyer, N. Leland, and R. Hokinson. Historical trend in alpha-particle induced soft error rates of the alpha™ microprocessor. In 39th Annual IEEE International Reliability Physics Symposium, pages 259–265, 2001.Google Scholar
  27. [27]
    P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the 2002 International Conference on Dependable Systems and Networks, pages 389–398, 2002.Google Scholar
  28. [28]
    J. Wallmark and S. Marcus. Minimum size and maximum packaging density of non-redundant semiconductor devices. In Proc. IRE, 50:286–298, 1962.Google Scholar
  29. [29]
    L. Wei, K. Roy, and V. K. De. Low voltage low power cmos design techniques for deep submicron ics. In VLSI Design, 2000. Thirteenth International Conference on, pages 24–29, 2000.Google Scholar
  30. [30]
    J. Ziegler. Terrestrial cosmic ray intensities. IBM Journal of Research and Development, 40(l):19–39, 1996.CrossRefGoogle Scholar

Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Vijay Degalahal
    • 1
  • R. Ramanarayanan
    • 1
  • Narayanan Vijaykrishnan
    • 1
  • Y. Xie
    • 1
  • M. J. Irwin
    • 1
  1. 1.Embedded and Mobile Computing Design CenterPennsylvania State UniversityUSA

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