Abstract
The paper addresses physical design automation methodologies and tools in which cells are generated on the fly as a form of contributing to power and time optimizations and improving the convergence of the design process. By not being restricted to cell libraries it is possible to implement any logic function defined at logic synthesis, including static CMOS complex gates – SCCG. The use of SCCG reduces the amount of transistors and helps to reduce wire length and static power. Main strategies for automatic layout generation, like transistor topology, contact and via management, body ties placement, power lines disposition and transistor sizing come into account. For both standard cell and automatic layout generation methodologies, a good set of placement and routing algorithms is needed. This work addresses convergence issues of the methodology as well, including some key strategies that help the development of efficient CAD tools that can find better layout solutions than those from traditional standard cell and fixed-die methodologies
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Reis, R., Güntzel, J., Johann, M. (2006). Physical Design Automation. In: Reis, R., Lubaszewski, M., Jess, J.A. (eds) Design of Systems on a Chip: Design and Test. Springer, Boston, MA. https://doi.org/10.1007/0-387-32500-X_5
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DOI: https://doi.org/10.1007/0-387-32500-X_5
Publisher Name: Springer, Boston, MA
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