Post-Fabrication Clock-Timing Adjustment Using Genetic Algorithms
To solve the problem of fluctuations in clock timing (also known as “clock skew” problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GA). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: (1) enhancement in clock frequencies leading to improved operational yields, (2) lower power supply voltages, while maintaining operational yield, and (3) reductions in design times. Two different LSIs have been developed; the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time. Furthermore, we also propose an adjustment algorithm that takes into account the ensured timing margins to cope with fluctuations in power supply voltage and clock frequency.
Key wordsclock-timing adjustment post-fabrication adjustment genetic algorithm improved operational yield clock enhancement lower power-supply voltage reduced design times reduced power dissipation
Unable to display preview. Download preview PDF.
- Deleganes, D., et al. 2002. Designing a 3GHz, 130nm, Pentium (R) 4 Processor. In Proc. of 2002 Symposium on VLSI Circuits, 130–133.Google Scholar
- Dike, C, et al. 2003. A Design for Digital, Dynamic Clock Deskew. In Symp. VLSI Circuits Dig., 21–24.Google Scholar
- Geannopoulos, G. and X. Dai. 1998. An Adaptive Digital Deskewing Circuit for Clock Distribution Networks. In ISSCC Dig. Tech. Papers, Feb. 1998, 400–401.Google Scholar
- Higuchi, T., et al. 2003. “Designers to Raise Yields, Manufacturers to Raise Design Efficiency: Part 2 Circuit Technology,” Nikkei Microdevices, No. 219, 38–45, Sep. 2003 (in Japanese).Google Scholar
- Holland, J. H. 1975. Adaptation in Natural and Artificial Systems. Ann Arbor, MI: Univ. of Michigan Press, 1975.Google Scholar
- Nedovic, N., V. Oklobdzija and W. Walker. 2003. A Clock Skew Absorbing Flip-Flop. In ISSCC Dig. Tech. Papers, Feb. 2003, 342–343.Google Scholar
- Rabaey, J., A. Chandrakasan and B. Nikolic. 2003. Digital Integrated Circuits 2nd Ed. New Jersey: Prentice Hall, 2003.Google Scholar
- Roth, E., et al. 2003. A Delay-line Based DCO for Multimedia Applications Using Digital Standard Cells Only. In ISSCC Dig. Tech. Papers, Feb. 2003, 442–443.Google Scholar
- Sakurai, T. 1999. “LSI design toward 2010 low-power technology,” Int. Conf. VLSI & CAD’ 99, 325–334.Google Scholar
- Takahashi, E., et al. 1999. An Evolvable-Hardware-based Clock Architecture towards GigaHz Digital Systems. In Proc. of AAAI GECCO’99 (Genetic Algorithm and Evolutionary Computation Conference), 1204–1210, July 1999.Google Scholar
- Takahashi, E., et al. 2003. A Post-Silicon Clock Timing Adjustment Using Genetic Algorithms. In Symp. VLSI Circuits Dig., 2003, 13–16.Google Scholar