Abstract
We present an asynchronous software and hardware architecture specifically suited for wireless sensor network nodes. To reduce power consumption and/or increase performances, some blocks go into hardware. The whole system is modelled using a unique asynchronous HDL before being partitioned. The software part that is executed on an asynchronous processor is then scheduled using a quasi-static scheduling and operates in an event-driven way with reactive hardware through an interface controller. We use an asynchronous analog to digital converter combined to a new approach in the non-uniform signal processing theory to obtain an entire event-driven platform. The use of asynchronous hardware allows to efficiently design a fine-grained dynamic power consumption control mechanism controlling Vdd (digital voltage scaling) and Vbb (bulk biasing) in order to manage the speed/power consumption trade-off and to go in a low-power idle mode state with very few static leakage. Finally, to increase the lifetime of the nodes, some scavenging techniques are added.
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© 2006 International Federation for Information Processing
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Buhrig, A., Renaudin, M., Barthel, D. (2006). Asynchrnous Architecture for Sensor Network Nodes. In: Al Agha, K., Guérin Lassous, I., Pujolle, G. (eds) Challenges in Ad Hoc Networking. Med-Hoc-Net 2005. IFIP International Federation for Information Processing, vol 197. Springer, Boston, MA. https://doi.org/10.1007/0-387-31173-4_30
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DOI: https://doi.org/10.1007/0-387-31173-4_30
Publisher Name: Springer, Boston, MA
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