2.8 Summary
This chapter presented an overview of the design and verification flow involved in the development of a digital integrated circuit. It discussed the main techniques used to verify such circuits, namely functional validation (by means of logic simulation) and formal verification, using a range of techniques.
We reviewed basic concepts and representations for Boolean functions and for sequential systems, and described how a logic simulator works. The models discussed in the earlier sections will be needed to present all the main techniques in the later chapters. The last part of the chapter was dedicated to skim over a range of formal verification techniques, and give a sense of this methodology through the presentation of symbolic FSM traversal. The next chapter covers in great detail another technique, symbolic simulation, and draws the similarities between that and reachability analysis.
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(2006). Design and Verification of Digital Systems. In: Scalable Hardware Verification with Symbolic Simulation. Springer, Boston, MA. https://doi.org/10.1007/0-387-29906-8_2
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