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References
“Test Coverage: What does it mean when a board test passes”, K. Hird, K. P. Parker and B. Follis, Proceedings, International Test Conference, 2002, pages 1066-1074.
“Opens Board Test Coverage: When is 99% Really 40%”, M. V. Tegethoff, K. P. Parker, K. Lee, Proceedings, International Test Conference, 1996, pages 333-339.
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149. 1 2001, IEEE Standards Board, 345 East 47th St. New York NY 10017, 2001.
“The Boundary-Scan Handbook”, 3rd Edition, Kenneth P. Parker, Kluwer Academic Publishers, Norwell Mass, 2003.
“Analog In-Circuit Component Measurements: Problems and Solutions”, D. T. Crook, Hewlett-Packard Journal, vol 30, No. 3, March 1979.
“Structure and Metrology for an Analog Testability Bus”, K. P. Parker, J. E. McDermid, S. Oresjo, Proceedings, International Test Conference, pp 309-322, Baltimore MD, Oct 1993.
“IEEE Standard for a Mixed Signal Test Bus”, IEEE Standard 1149. 4-1999, IEEE Standards Board, 345 East 47th St. New York NY 10017, 1999.
“Limited Access Testing: Ability and Requirements”, J. McDermid, Proceedings, NEPCON 1998, Anaheim CA, Feb 1998.
“Solving Limited Access Constraints in ICT”, J. McDermid, Electronics Engineer, July 1998.
“Limited Access Testing: 1149. 4 Instrumentation and Methods”, J. McDermid, Proceedings, International Test Conference, Washington DC, Oct 1998.
“Measuring Thermal Rises Due to Digital Device Overdriving”, G. S. Bushanam et al, Proceedings, International Test Conference, pp 400-407, Philadelphia PA, Oct 1984.
“SAFEGUARD In-Circuit, a Description of HP s Safe Implementation of Digital In-, Circuit Test”, Product Note3065-2, Hewlett-Packard Manufacturing Test Division, Loveland CO, Sept 1985.
“Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?”, K. P. Parker, Proceedings, International Test Conference, pp 1268-1276, Charlotte NC, Sept 2003.
“IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks”, IEEE Standard 1149. 6-2003, IEEE Standards Board, 345 East 47th St. New York NY, 10017, 2003.
“A New Probing Technique for High-Speed/High-Density Printed Circuit Boards”, K. P. Parker, Proceedings, International Test Conference, pp 365-374, Charlotte NC, Oct 2004.
“On-chip Mixed-Signal Test Structures Re-used for Board Test”, R. Schuttert, D. C. L. van Geest and A. Kumar, Proceedings, International Test Conference, pp 375-383, Charlotte NC, Oct 2004.
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© 2006 Springer
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Parker, K.P. (2006). Loaded Board Testing. In: Gizopoulos, D. (eds) Gizopoulos / Advances in ElectronicTesting. Frontiers in Electronic Testing, vol 27. Springer, Boston, MA. https://doi.org/10.1007/0-387-29409-0_11
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