Abstract
The paper reports on some experiments with implementing positional digital image filters using field programmable devices. It demonstrates that a single field programmable device may be used to build such a filter. By using extensive pipelining in the design, the filter can achieve performance of 50 million pixels per second (using Xilinx XC4000E devices) and over 120 MHz (in case of Spartan-3 devices). These results were obtained using automatic synthesis from VHDL descriptions, avoiding any direct manipulation in the design.
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© 2005 Springer Science+Business Media, Inc.
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Caban, D. (2005). FPGA Implementation of Positional Filters. In: Design of Embedded Control Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28327-7_21
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DOI: https://doi.org/10.1007/0-387-28327-7_21
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-23630-8
Online ISBN: 978-0-387-28327-2
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