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Verification Guidelines

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Systemverilog for Verification
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1.17 Conclusion

The continuous growth in complexity of electronic designs requires a modern, systematic, and automated approach to creating testbenches. The cost of fixing a bug grows by 10x as a project moves from each step of specification to RTL coding, gate synthesis, fabrication, and finally into the user’s hands. Directed tests only test one feature at a time and cannot create the complex stimulus and configurations that the device would be subjected to in the real world. To produce robust designs, you must use constrained-random stimulus combined with functional coverage to create the widest possible range of stimulus.

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© 2006 Springer Science+Business Media, LLC

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(2006). Verification Guidelines. In: Systemverilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/0-387-27038-8_1

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  • DOI: https://doi.org/10.1007/0-387-27038-8_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-27036-4

  • Online ISBN: 978-0-387-27038-8

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