3.3 Summary
Reconfigurable logic has found its way into virtually every part of the parallel processing hierarchy. Millions of system gates are available for Instructionlevel parallelism within the reconfigurable fabric. By sharing registers or internal busses with a conventional microprocessor, co-processor performance is even more accelerated through low latency, high bandwidth communication between processor and reconfigurable logic. In the I/O model, an FPGA array can process large granularity compute- and/or data-intensive tasks for the processor. Finally, by aggregating collections of FPGAs either as a standalone system or as part of a reconfigurable cluster supercomputer, parallelism can be exploited at a very large scale.
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© 2005 Springer
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(2005). Reconfigurable Computing Systems. In: Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/0-387-26106-0_3
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DOI: https://doi.org/10.1007/0-387-26106-0_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-26105-8
Online ISBN: 978-0-387-26106-5
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