This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
M. Ismail and T. Fiez, eds., Analog VLSI: Signal and Information Processing, McGraw-Hill Publishing Company, Inc., New York, 1994.
B. Koenemann, “Creature from the deep submicron lagoon”, Invited Lecture, 10th Workshop Test Methods and Reliability of Circuits and Systems, March 1998.
A.N. Airapetian and J.F. McDonald, “Improved test set generation algorithm for combinational logic control”, Digest of Papers, 9th Annual International Symposium on Fault-Tolerant Computing, pp. 133–136, June 1979.
E.B. Eichelberger and T.W. Williams, “A logic design structure for LSI testing”, Proceedings, IEEE/ACM 14th Design Automation Conference (DAC 1977), pp. 462–468, June 1977.
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990 (includes IEEE Standard 1149.1a-1993), The IEEE, Inc., New York, October 1993.
B. Koenemann, J. Mucha and G. Zwiehoff, “Built-in logic block observation techniques”, Proceedings, 1979 IEEE International Test Conference, pp. 37–41, October 1979.
“A D&T roundtable mixed-signal design and test”, IEEE Design & Test of Computers, Vol. 10, pp. 80–86, September 1993.
J.P. Roth, “Diagnosis of automata failures: a calculus and a method”, IBM Journal of Research and Development, Vol. 10, pp. 278–291, July 1966.
P. Goel, “An implicit enumeration algorithm to generate tests for combinational circuits”, IEEE Transactions on Computers, Vol. C-30, pp. 215–222, March 1981.
D.M.W. Leenaerts, “TOPICS: a new hierarchical design tool using an expert system and interval analysis”, Proceedings, 17th European Solid State Circuits Conference (ESSIRC 1991), pp. 37–40, September 1991.
G. Debyser and G. Gielen, “Efficient analog circuit synthesis with simultaneous yield and robustness optimisation”, Digest of Papers, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-98), pp. 308–311, November 1998.
M. Krasnicki, R. Phelps, R.A. Rutenbar and L.R. Carley, “MAELSTROM: efficient simulation-based synthesis for custom analog cells”, Proceedings, IEEE/ACM 36th Design Automation Conference (DAC 1999), pp. 945–950, June 1999.
S. Ohr, “Synthesis proves to be holly grail for analog EDA”, EE Times at http://www.eetimes.com, June 1999.
T.W. Williams, “Design for testability”, Computer Design Aids for VLSI Circuits (P. Antogneti, D. O. Peterson, and H de Man, eds.), NATO AIS Series, Martinus Nijhoff Publishers, The Netherlands, pp. 359–415, 1986.
IEEE Standard for a Mixed-Signal Test Bus (Draft 18), The Proposed IEEE Standard P1149.4, The IEEE, Inc., New York, June 1997.
W. Maly, H.T. Heineken, J. Khare and P.K. Nag, “Design-manufacturing interface: part I-vision”, Proceedings, Design Automation and Test in Europe Conference and Exhibition (DATE 1998), pp. 550–556, February 1998.
L.S. Milor, “A tutorial introduction to research on analog and mixed-signal circuit testing”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, pp. 1389–1407, October 1998.
P. Duhamel and J.C. Rault, “Automatic test generation techniques for analog circuits and systems: A review”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 441–440, July 1979.
J.W. Bandler and A.E. Salama, “Fault diagnosis of analog circuits”, Proceedings of the IEEE, Vol. 73, pp. 1279–1325, August 1985.
B. Vinnakota, Analog and Mixed-Signal Test, Prentice-Hall, Inc., New Jersey, 1998.
M. Burns and G.W. Roberts, An Introduction to Mixed-Signal IC Test and Measurements, Oxford University Press, New York, 2001.
R.S. Berkowitz, “Conditions for network-element-value solvability”, IRE Transactions on Circuit Theory, Vol. CT-9, pp. 24–29, March 1962.
R. Saeks, S.P. Singh and R-W. Liu, “Fault isolation via component simulation”, IEEE Transactions on Circuit Theory, Vol. CT-19, pp. 634–640, November 1972.
R.M. Biernacki and J.W. Bandler, “Postproduction parameter identification of analog circuits”, Proceedings, IEEE International Symposium on Circuits and Systems, pp. 1082–1086, April 1980.
R.M. Biernacki and J.A. Starzyk, “Sufficient test conditions for parameter identification of analog circuits based on voltage measurement”, Proceedings, European Conference on Circuit Theory and Design, Vol. 2, pp. 233–241, September 1980.
T.N. Trick, W. Mayeda and A.A. Sakla, “Calculation of parameter values from node voltage measurement”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 466–474, July 1979.
N. Navid and A.N. Willson, Jr., “A theory and an algorithm for analog circuit fault diagnosis”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 440–456, July 1979.
T. Ozawa and Y. Kajitani, “Diagnosability of linear active network”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp 485–489, July 1979.
J.A. Starzyk, R.M. Biernacki and J.W. Bandler, “Evaluation of faulty elements within linear subnetworks”, International Journal of Circuit Theory and Applications, Vol. 12, pp. 23–27, January 1984.
T. Ozawa, S. Shinoda and M. Yamada, “An equivalent-circuit transformation and its application to network-element-value calculation”, IEEE Transactions on Circuits and Systems, Vol. CAS-30, pp. 432–441, July 1983.
V. Visvanathan and A. Sangiovanni-Vincentalli, “Diagnosability of nonlinear circuits and systems-part I: the dc case”, IEEE Transactions on Circuits and Systems, Vol. CAS-28, pp. 1093–1102, November 1981.
N. Sen and R. Saeks, “A measure of testability and its applications to test point selection theory”, Proceedings, 20th Midwest Symposium on Circuits and Systems, pp. 576–583, August 1977.
N. Sen and R. Saeks, “Fault diagnosis for linear systems via multifrequency measurements”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 457–465, July 1979.
H.M.S. Chen and R. Saeks, “A search algorithm for the solution of multifrequency fault diagnosis equations”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 589–594, July 1979.
R.W. Priester and J.B. Clary, “New Measures of testability and test complexity for linear analog failure analysis”, IEEE Transactions on Circuits and Systems, Vol. CAS-28, pp. 1088–1092, November 1981.
L. Rapisarda and R. DeCarlo, “Analog multifrequency fault diagnosis”, IEEE Transactions on Circuits and Systems, Vol. CAS-30, pp. 223–234, April 1983.
A. Abderrahman, E. Cerny and B. Kaminska, “Optimization-based multifrequency test generation for analog circuits”, Journal of Electronic Testing: Theory and Applications, Vol. 9, pp. 59–73, August/October 1996.
H-T. Sheu and Y-H. Chang, “The relaxation pseudocircuit method for analog fault diagnosis”, International Journal of Circuit Theory and Application, Vol. 24, pp. 201–221, March/April 1996.
R. Saeks, A. Sangiovanni-Vincentalli and V. Visvanathan, “Diagnosability of nonlinear circuits and systems-part II: dynamical systems”, IEEE Transactions on Circuits and Systems, Vol. CAS-28, pp. 1103–1108, November 1981.
V. Visvanathan and A. Sangiovanni-Vincentalli, “A computational approach for the diagnosability of dynamical circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-3, pp. 165–171, July 1984.
H. Dai and T.M. Souders, “Time-domain testing strategies and fault diagnosis for analog systems”, IEEE Transactions on Instrumentation and Measurement, Vol. 39, pp. 157–162, February 1990.
A.E. Salama and F.Z. Amer, “Parameter identification approach to fault diagnosis of switched capacitor circuits”, IEE Proceedings-G, Circuits, Devices and Systems, Vol. 139, pp. 467–472, August 1992.
A. Walker, W.E. Alexander and P.K. Lala, “Fault diagnosis in analog circuits using element modulation”, IEEE Design & Test of Computers, Vol. 9, pp. 19–29, March 1992.
Z.F. Huang, C-S. Lin and R-W. Liu, “Node-fault diagnosis and a design of testability”, IEEE Transaction on Circuits and Systems, Vol. CAS-30, pp. 257–265, May 1983.
A. Materka and M. Strzelecki, “Parametric testing of mixed-signal circuits by ANN processing of transient responses”, Journal of Electronic Testing: Theory and Applications, Vol. 9, pp. 187–202, August/October 1996.
S. Cherubal and A. Chatterjee, “Parametric fault diagnosis for analog systems using functional mapping 1”, Proceedings, Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), pp. 195–200, March 1999.
M. Pronath, V. Gloeckel and H. Graeb, “A parametric test method for analog components in integrated mixed-signal circuits”, Digest of Papers, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2000), pp. 557–561, November 2000.
Z. Guo and J. Savir, “Algorithm-based fault detection of analog linear time-invariant circuits”, Proceedings, 18th IEEE Instrumentation and Measurement Technology Conference (IMTC 2001), Vol. 1, pp. 49–54, May 2001.
G. Temes, “Efficient methods of fault simulation”, Proceedings, 20th Midwest Symposium on Circuit and Systems, pp. 191–194, August 1977.
W.J. Dejka, “A review of measures of testability for analog systems”, Proceedings, International Automatic Testing Conference (AUTOTESTCON 1977), November 1977.
A.A. Skala, E.I. El-Masry and T.N. Trick, “A sensitivity algorithm for fault detection in analog circuits”, Proceedings, IEEE International Symposium on Circuits and Systems, pp. 1075–1077, April 1980.
M. Slamani and B. Kaminska, “Analog circuit fault diagnosis based on sensitivity computation and functional testing”, IEEE Design & Test of Computers, Vol. 9, pp. 30–39, March 1992.
C-S. Lin, Z.F. Huang and R-W. Liu, “Topological conditions for single-branch-fault”, IEEE Transactions on Circuits and Systems, Vol. CAS-30, pp. 376–381, June 1983.
H. Maeda, Y. Ohta, S. Kodama and S. Takeda, “Fault diagnosis of non-linear systems: graphical approach to detectability, distinguishability and diagnosis algorithm”, International Journal of Circuit Theory and Applications, Vol. 14, pp. 195–209, July 1986.
T. Ozawa, J.W. Bandler and A.E. Salama, “Diagnosability in the decomposition approach for fault location in large analog networks”, IEEE Transactions on Circuits and Systems, Vol. CAS-32, pp. 415–416, April 1985.
J.A. Starzyk and H. Dai, “A decomposition approach for testing large analog networks”, Journal of Electronic Testing: Theory and Applications, Vol. 3, pp. 181–195, October 1992.
D. Ying and H. Yigang, “On the application of artificial neural networks to fault diagnosis in analog circuits with tolerances”, Proceedings, 5th International Conference on Signal Processing (WCCC-ICSP 2000), Vol. 3, pp. 1639–1642, August 2000.
D. Ying, H. Yigang and S. Yichuang, “Fault diagnosis of analog circuits with tolerances using artificial neural networks”, Proceedings, 2000 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2000), pp. 292–295, December 2000.
G.N. Stenbakken and T.M. Souders, “Ambiguity groups and testability”, IEEE Transactions on Instrumentation and Measurement, Vol. 38, pp. 941–947, October 1989.
G.H. Hemink, B.W. Meijer and H.G. Kerkhof, “Testability analysis of analog systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, pp. 573–583, June 1990.
M. Slamani and B. Kaminska, “Fault observability analysis of analog circuits in frequency domain”, IEEE Transactions on Circuits and Systems, Vol. 43, pp. 134–139, February 1996.
J.A. Starzyk, J. Pang, S. Manetti, M.C. Piccirilli and G. Fedi, “Finding ambiguity groups in low testability analog circuits”, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 47, pp. 1125–1137, August 2000.
N.S.C. Babu, “Efficient techniques for fault diagnosis of analog circuits using dictionary approach”, Ph.D. Dissertation, Indian Institute of Technology, Delhi, 1997.
V.C. Prasad and N.S.C. Babu, “Selection of test nodes for analog fault diagnosis in dictionary approach”, IEEE Transactions on Instrumentation and Measurement, Vol. 49, pp. 1289–1297, December 2000.
J.A. Soares Augusto and C.F. Beltran Almeida, “Analog fault diagnosis in nonlinear DC circuits with an evolutionary algorithm”, Proceedings, 2000 Congress on Evolutionary Computation (CEC2000), Vol. 1, pp. 609–616, July 2000.
J. Viehland and T. Fairbanks, “Parallel analog functional test”, Proceedings, 2001 IEEE Autotestcon (IEEE Systems Readiness Technology Conference), pp. 616–624, August 2001.
G.O. Martens and J.D. Dyck, “Fault identification in electronic circuits with the aid of bilinear transformation”, IEEE Transactions on Reliability, Vol. R-21, pp. 99–104, May 1972.
C. Morgan and D.R. Towill, “Application of the multiharmonic Fourier filter to nonlinear system fault location”, IEEE Transactions on Instrumentation and Measurement, Vol. IM-26, pp. 164–169, June 1977.
K.C. Varghese, J.H. Williams and D.R. Towill, “Simplified ATPG and analog fault location via a clustering and separability technique”, IEEE Transaction on Circuits and Systems, Vol. CAS-26, pp. 496–505, July 1979.
P.M. Lin and Y.S. Elcherif, “Analogue circuits fault dictionary-new approaches and implementation”, International Journal of Circuit Theory and Applications, Vol. 13, pp.149–172, April 1985.
S. Seshu and R. Waxman, “Fault isolation in conventional linear systems-a feasibility study”, IEEE Transactions on Reliability, Vol. R-15, pp. 11–16, March 1966.
M.J. Macleod, “Comparison of methods of parameter estimation using pseudo random binary sequences”, Electronics Letters, Vol. 9, pp. 342–343, July 1973.
H.H. Schreiber, “Fault dictionary based upon stimulus design”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 529–537, September 1979.
F-L. Wang and H.H. Schreiber, “A pragmatic approach to automatic test generation and failure isolation of analog systems”, IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 584–585, July 1979.
A. Balivada, J. Chen and J.A. Abraham, “Analog testing with time response parameters”, IEEE Design & Test of Computers, Vol. 13, pp. 18–25, Summer 1996.
A. Balivada, H. Zheng, N. Nagi, A. Chatterjee and J.A. Abraham, “A unified approach for fault simulation of linear mixed signal circuits”, Journal of Electronic Testing: Theory and Applications, Vol. 9, pp. 29–41, August/October 1996.
M.A. Al-Qutayri and P.R. Shepherd, “Go/no-go testing of analogue macros”, IEE Proceedings-G, Circuits, Devices and Systems, Vol. 139, pp. 534–540, August 1992.
W. Hochwald and J.D. Bastian, “A dc approach for analog fault dictionary determination”, IEEE Transactions on Circuits and systems, Vol. CAS-26, pp. 523–529, July 1979.
A. Pahwa and R.A. Rohrer, “Band faults: Efficient approximations to fault bands for the simulation before fault diagnosis of linear circuits”, IEEE Transactions on Circuits and Systems, Vol. CAS-29, pp. 81–88, February 1982.
G. Rutkowski, “A two stage neural network DC fault dictionary”, Proceedings, 1994 IEEE International Symposium on Circuits and Systems (ISCAS’94), Vol. 6, pp. 299–302, June 1994.
D.K. Papakostas and A.A. Hatzopoulos, “Supply current testing in linear bipolar ICs”, Electronics Letters, pp. 128–130, January 1994.
A.A. Hatzopoulos, S. Siskos and T. Laopoulos, “Current conveyor based test structures for mixed-signal circuits”, IEE Proceedings, Circuits, Devices and Systems, Vol. 144, pp. 213–217, August 1997.
S.S. Somayajula, E. Sanchez-Sinencio and J.P. Gyvez, “Analog fault diagnosis based on ramping power supply current signature clusters”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 43, pp. 703–712, October 1996.
A.K.B. Aain, A.H. Bratt and A.P. Dorey, “Testing analog circuits by power supply voltage control”, Electronics Letters, Vol. 30, pp. 214–215, February 1994.
A.K.B. Aain, A.H. Bratt and A.P. Dorey, “Testing analog circuits by AC power supply voltage”, Proceedings, 9th International Conference on VLSI Design, pp. 238–241, January 1996.
W.M. Lindermeir, T.J. Vogels and H.E. Graeb, “Analog test design with I/sub DD/ measurements for the detection of parametric and catastrophic faults”, Proceedings, Design Automation and Test in Europe Conference and Exhibition (DATE 1998), pp.822–827, February 1998.
H. Manhaeve, J. Verfaillie, B. Straka and J.P. Cornil, “Application of supply current testing to analogue circuits, towards a structural analogue test methodology”, Proceedings, European Test Workshop 1999, pp. 51–56, May 1999.
D. Matthes and J. Ford, “Technique for testing a very high speed mixed signal read channel design”, Proceedings, 2000 IEEE International Test Conference, pp. 965–970, October 2000.
A.A. Hatzopoulos and J.M. Kontoleon, “A new approach for automatic fault diagnosis in analog circuits”, International Journal of Circuit Theory and Applications, Vol. 18, pp. 387–400, 1989.
S. Manetti, M.C. Piccirilli and A. Liberatore, “Automatic test point selection for linear analog network fault diagnosis”, Proceedings, IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 25–28, May 1990.
A. Bernieri and G. Betta, “On-line fault detection and diagnosis obtained by implementing neural algorithms on a digital signal processor”, IEEE Transactions on Instrumentation and Measurement, Vol. 45, pp. 894–899, October 1996.
S. Yu, B.W. Jervis, K.R. Eckersall, I.M. Bell, A.G. Hall and G.E. Taylor, “Neural network approach to fault diagnosis in CMOS Op-Amps with gate oxide short faults”, Electronic letters, Vol. 30, pp. 695–696, April 1994.
A. Wu and J. Meador, “Measurement selection for parametric IC fault diagnosis”, Journal of Electronic Testing: Theory and Applications, Vol. 5, pp. 9–18, August 1994.
R. Spina and S.J. Upadhyaya, “Linear circuit fault diagnosis using neuromorphic analyzers”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 44, pp. 188–196, March 1997.
A.I. Nissar and S.J. Upadhyaya, “Fault diagnosis of mixed signal VLSI systems using artificial neural networks”, Proceedings, South-West Symposium on Mixed-Signal Design, pp. 93–98, April 1999.
Z.R. Yang, M. Zwolinski, C.D. Chalk and A.C. Williams, “Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, pp. 142–150, January 2000.
Y. Maidon, B.W. Jervis, N. Dutton and S. Lesage, “Diagnosis of multifaults in analog circuits using multilayer perceptrons”, IEE Proceedings, Circuits, Devices and Systems, Vol. 144, pp. 149–154, June 1997.
M.A. El-Gamal and M.F. Abu El-Yazeed, “A combined clustering and neural network approach for analog multiple hard fault classification”, Journal of Electronic Testing: Theory and Application, Vol. 14, pp. 207–217, June 1999.
L. Carro and M. Negreivos, “Efficient test methodology based on adaptive algorithm”, Proceeding, 35th Design Automation Conference (DAC98), pp. 230–233, June 1998.
E.F. Cota, M. Negreivos, L. Carro and M. Lubaszewaski, “A new adaptive analog test and diagnosis system”, IEEE Transactions on Instrumentation and Measurement, Vol. 49, pp. 223–227, April 2000.
Y-T. Chen and C. Su, “Test waveform shaping in mixed signal test bus by preequalization”, Proceedings, 19th IEEE VLSI Test Symposium (VTS 2001), pp. 260–265, April–May 2001.
M. Aminian and F. Aminian, “A comprehensive examination of neural network architectures for analog fault diagnosis”, Proceedings, INNS-IEEE International Joint Conference on Neural Networks (IJCNN2001), Vol. 3, pp. 2304–2309, July 2001.
M. Favalli, P. Olivo and B. Ricco, “A probabilistic fault model for analog faults in CMOS circuits”, Proceedings, European Design Automation Conference (EDAC), pp. 85–88, February 1991.
B.R. Epstein, M. Czigler and S.R. Miller, “Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp. 103–113, January 1993.
G. Devarayanadurg, P. Goteti and M. Soma, “Hierarchy based statistical fault simulation of mixed-signal ICs”, Proceedings, 1996 IEEE International Test Conference, pp. 521–527, October 1996.
G. Devarayanadurg, M. Soma, P. Goteti and S.D. Huynh, “Test set selection for structural faults in analog ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, pp. 1026–1039, July 1999.
G. Gielen, Z. Wang and W. Sansen, “Optimal fault detection for analog circuits under manufacturing tolerances”, Electronics Letters, Vol. 32, pp.33–34, January 1996.
Z. Wang, G. Gielen and W. Sansen, “Probabilistic fault detection and the selection of measurements for analog integrated circuits”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, pp. 862–872, September 1998.
S. Ozev, I. Bayraktaroglu and A. Orailogiu, “Test synthesis for mixed-signal SOC paths”, Proceedings, Design, Automation and Test in Europe Conference and Exhibition (DATE 2000), pp. 28–33, March 2000.
Rights and permissions
Copyright information
© 2005 Springer
About this chapter
Cite this chapter
(2005). Introduction. In: Fault Diagnosis of Analog Integrated Circuits. Frontiers in Electronic Testing, vol 30. Springer, Boston, MA. https://doi.org/10.1007/0-387-25743-8_1
Download citation
DOI: https://doi.org/10.1007/0-387-25743-8_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-25742-6
Online ISBN: 978-0-387-25743-3
eBook Packages: EngineeringEngineering (R0)