Skip to main content
SpringerLink
Log in

Other Building Blocks of PLL

  • Chapter
Book cover CMOS PLL Synthesizers: Analysis and Design

Part of the book series: The International Series in Engineering and Computer Science ((SECS,volume 783))

  • 2271 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717–724, May 1999

    Article  Google Scholar 

  2. D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, pp. 896–909, June 2001

    Article  Google Scholar 

  3. M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1018–1024, July 2001

    Article  Google Scholar 

  4. F. Dulger and E. Sánchez-Sinencio, “Design trade-offs of a symmetric linearized CMOS LC VCO,” in Proc. ISCAS, vol. 4, Phoenix, AZ, May 2002, pp. 397–400

    Google Scholar 

  5. L. Lin, “Design techniques for high performance integrated frequency synthesizers for multi-standard wireless communication applications,” Ph.D. dissertation, University of California at Berkeley, CA, Dec. 2000

    Google Scholar 

  6. J. Rogers, J. Macedo, and C. Plett, “The effect of varactor nonlinearity on the phase noise of completely integrated VCOs,” IEEE J. Solid-State Circuits, vol. 35, pp. 1360–1367, Sept. 2000

    Article  Google Scholar 

  7. A. Porret, T. Melly, C. Enz, and E, Vittoz, “Design of high-g varactors for low-power wireless applications using a standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, pp. 337–345, Mar. 2000

    Article  Google Scholar 

  8. F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal oxide semiconductor varactor,” IEEE Electron Device Lett., vol. 20, pp. 164–166, Apr. 1999

    Article  Google Scholar 

  9. P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905–910, June 2000

    Article  Google Scholar 

  10. T. Soorapanth, C. Yue, D. Shaeffer, T. Lee, and S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in 1998 Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 22–23

    Google Scholar 

  11. N. Nguyen and R. Meyer, “Si IC-compatible inductors and LC passive filters,” IEEE J. Solid-State Circuits, vol. 25, pp. 1028–1031, Aug. 1990

    Article  Google Scholar 

  12. J. Chang, A. Abidi, and M. Gaitan, “Large suspended inductors on silicon and their use in a 2-µm CMOS RF amplifier,” IEEE Electron Device Lett., vol. 14, pp. 246–248, May 1993

    Article  Google Scholar 

  13. P. Gray and R. Meyer, “Future directions in silicon IC’s for RF personal communications,” in Proc.IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1995, pp. 83–90

    Google Scholar 

  14. J. Craninckx and M. Steyaert, “Low noise voltage-controlled oscillators using enhanced LC-tanks,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 794–804, Dec. 1995

    Article  Google Scholar 

  15. C. Yue, C. Ryu, J. Lau, T. Lee, and S. Wong, “A physical model for planar spiral inductors on silicon,” International Electron Devices Meeting, Dec. 1996, pp. 155–158

    Google Scholar 

  16. J. Long and M. Copeland, “The modeling, characterization, and design of monolithic inductors for silicon RF IC’s,” IEEE J. Solid-State Circuits, vol. 32, pp. 357–369, Mar. 1997

    Article  Google Scholar 

  17. A. Niknejad and R. Meyer, “Analysis, design, and optimization of spiral inductors and transformers for Si RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp. 1470–1481, Oct. 1998

    Article  Google Scholar 

  18. W. Wu, Y. Chan, and C. Wang, “An enhanced model for planar inductors in CMOS technology,” Int. Symp. VLST Tech. Syst. Application, June 1999, pp. 143–146

    Google Scholar 

  19. Y. Koutsoyannopoulos and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 699–713, Aug. 2000

    Article  Google Scholar 

  20. C. Yue and S. Wong, “On-chip spiral inductors with patterned ground shields for Sibased RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp. 743–752, May 1998

    Article  Google Scholar 

  21. J. Burghartz, D. Edelstein, M. Soyeur, H. Ainspan, and K. Jenkins, “RF circuit design aspects of spiral inductors on silicon,” IEEE J. Solid-State Circuits, vol. 33, pp. 2028–2034, Dec. 1998

    Article  Google Scholar 

  22. C. Lo and H. Luong, “A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications,” IEEE J. Solid-State Circuits, vol. 37, pp. 459–470, Apr. 2002

    Article  Google Scholar 

  23. K. O, “Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies,” IEEE J. Solid-State Circuits, vol. 33, pp. 1249–1252, Aug. 1998

    Article  Google Scholar 

  24. J. Craninckx and M. Steyaert, “A 1.8-GHz low-phase-noise voltage-controlled oscillator with prescaler,” IEEE J. Solid-State Circuits, vol. 30, pp. 1474–1482, Dec. 1995

    Article  Google Scholar 

  25. C. Lo, “A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications,” Master thesis, The Hong Kong University of Science and Technology, China, Jan. 2000

    Google Scholar 

  26. D. Leeson, “A simple model of feedback oscillator noises spectrum,” Proc. IEEE, vol. 54, pp. 329–330, Feb. 1966

    Google Scholar 

  27. B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331–343, Mar. 1996

    Article  Google Scholar 

  28. A. Hajimiri and T. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179–194, Feb. 1998

    Article  Google Scholar 

  29. —, “Corrections to ‘A general theory of phase noise in electrical oscillators’,” IEEE J. Solid-State Circuits, vol. 33, p. 928, June 1998

    Article  Google Scholar 

  30. A. Hajimiri, S. Limotyrakis, and T. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999

    Article  Google Scholar 

  31. T. Lee and A. Hajimiri, The Design of Low Noise Oscillators. Boston, MA: Kluwer, 1999

    Google Scholar 

  32. —, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, pp. 326–336, Mar. 2000

    Google Scholar 

  33. Y. Ou, N. Barton, R. Fetche, N. Seshan, T. Fiez, U. Moon, and K. Mayaram, “Phase noise simulation and estimation methods: A comparative study,” IEEE Trans. Circuits Syst. II, vol.49, pp. 635–638, Sept. 2002

    Article  Google Scholar 

  34. A. Demir, A. Mehrotra, and J. Roychowdhury, “Phase noise in oscillators: a unifying theory and numerical methods for characterization,” IEEE Trans. Circuits Syst. I, vol. 47, pp. 655–674, May 2000

    Article  Google Scholar 

  35. A. Demir, “Phase noise and timing jitter in oscillators with colored-noise sources,” IEEE Trans. Circuits Syst. I, vol. 49, pp. 1782–1791, Dec. 2002

    Article  Google Scholar 

  36. F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 56–62, Jan. 1999

    Article  Google Scholar 

  37. B. Kim, T. Weigandt, and P. Gray, “PLL/DLL system noise analysis for low jitter clock synthesizer design,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, May 1994, pp. 31–34

    Article  Google Scholar 

  38. W. Edson, “Noise in oscillators,” Proc. IRE, vol. 48, pp. 1454–1466, Aug. 1960

    Google Scholar 

  39. J. Mullen, “Background noise in nonlinear oscillators,” Proc. IRE, vol. 48, pp. 1467–1477, Aug. 1960

    Google Scholar 

  40. P. Grivet and A. Blaquiere, “Nonlinear effects of noise in electronic clocks,” Proc. IEEE, vol. 51, pp. 1606–1614, Nov. 1963

    Article  Google Scholar 

  41. E. Hafner, “The effects of noise in oscillators,” Proc. IEEE, vol. 54, pp. 179–198, Feb. 1966

    Google Scholar 

  42. A. Abidi and R. Meyer, “Noise in relaxation oscillators,” IEEE J. Solid-State Circuits, vol. 18, pp. 794–802, Dec. 1983

    Article  Google Scholar 

  43. H. Siweris and B. Schieck, “Analysis of noise upconversion in microwave FET oscillators,” IEEE Trans. Microwave Theory Tech., vol. 33, pp. 233–241, Jan. 1985

    Article  Google Scholar 

  44. J. McNeill, “Jitter in ring oscillators,” IEEE J. Solid-State Circuits, vol. 32, pp. 870–879, June 1997

    Article  Google Scholar 

  45. F. Herzel, “An analytical model for the power spectral density of a voltage-controlled pscillator and its analogy to the laser linewidth theory,” IEEE Trans. Circuits Syst. I, vol. 45, pp. 904–908, Sept. 1998

    Article  Google Scholar 

  46. C. Samori, A. Lacaita, F. Villa, and F. Zappa, “Spectrum folding and phase noise in LC tuned oscillators,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 781–790, July 1998

    Article  Google Scholar 

  47. S. Gierkink, E. Klumperink, A. van del Wel, G. Hoogzaad, E. van Tuijl, and B. Nauta, “Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 1022–1025, July 1999

    Article  Google Scholar 

  48. E. Klumperink, S. Gierkink, A. van del Wel, and B. Nauta, “Reducing MOSFET 1/f noise and power consumption by switched biasing,” IEEE J. Solid-State Circuits, vol. 35, pp. 994–1001, July 2000

    Article  Google Scholar 

  49. Q. Huang, “Phase-noise-to-carrier ratio in LC oscillators,” IEEE Trans. Circuits Syst. I, vol. 47, pp. 965–980, July 2000

    Article  Google Scholar 

  50. S. Levantino, C. Samori, A. Bonfanti, S. Gierkink, A. Lacaita, and V. Boccuzzi, “Frequency dependance on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE J. Solid-State Circuits, vol. 37, pp. 1003–1011, Aug. 2002

    Article  Google Scholar 

  51. L. Dai and R. Harjani, “Design of low-phase-noise CMOS ring oscillators,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 328–338, May 2002

    Google Scholar 

  52. F. Herzel, M. Pierschel, P. Weger, and M. Tiebout, “Phase noise in a differential CMOS voltage-controlled oscillator for RF applications,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 11–15, Jan. 2000

    Article  Google Scholar 

  53. B. Muer, M. Borremans, M. Steyaert, and G. Puma, “A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization,” IEEE J. Solid-State Circuits, vol. 35, pp. 1034–1038, July 2000

    Article  Google Scholar 

  54. K. Kouznetsov and R. Meyer, “Phase noise in LC oscillators,” IEEE J. Solid-State Circuits, vol. 37, pp. 1244–1248, Aug. 2000

    Article  Google Scholar 

  55. C. Hung and K. O, “A packaged 1.1-GHz CMOS VCO with phase noise of — 126dBc/Hz at 600-kHz offset,” IEEE J. Solid-State Circuits, vol. 35, pp. 100–103, Jan. 2000

    Article  Google Scholar 

  56. —, “A 1.24-GHz monolithic CMOS VCO with phase noise of −137 dBc/Hz at a 3-MHz offset,” IEEE Microwave Guided Wave Lett., vol. 9, pp. 111–113, Mar. 1999

    Article  Google Scholar 

  57. E. Hegazi, H. Sjoland, and A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, pp. 1921–1930, Dec. 2001

    Article  Google Scholar 

  58. C. Yang and S. Yuan, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE J. Solid-State Circuits, vol. 35, pp. 1445–1452, Oct. 2000

    Article  Google Scholar 

  59. C. Lo and H. Luong, “A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications,” IEEE J. Solid-State Circuits, vol. 37, pp. 459–470, Apr. 2002

    Article  Google Scholar 

  60. S. Kim, K. Lee, Y. Moon, D. Jeong, Y. Choi, and H. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691–700, Mar. 1997

    Article  Google Scholar 

  61. J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62–70, Feb. 1989

    Article  Google Scholar 

  62. H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, “A 1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase detector,” IEICE Trans. Electron., vol. E78-C, pp. 381–388, Apr. 1995

    Google Scholar 

  63. H. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE J. Solid-State Circuits, vol. 33, pp. 295–299, Feb. 1998

    Article  Google Scholar 

  64. S. Kim, K. Lee, Y. Moon, D. Jeong, Y. Choi, and H. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using lower jitter PLL,” IEEE J. Solid-State Circuits, vol. 33, pp. 691–700, May 1997

    Google Scholar 

  65. D. Boerstler and K. Jenkins, “A phase-locked loop clock generator for a 1 GHz microprocessor,” in Proc. IEEE Symp. VLSI Circuits, 1998, pp. 212–213

    Google Scholar 

  66. P. Larsson, “A 2∼1600-MHz CMOS clock recovery PLL with low Vdd capacity,” IEEE J. Solid-State Circuits, vol. 34, pp. 1951–1960, Dec. 1999

    Article  Google Scholar 

  67. J. Craninckx and M. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp. 2054–2065, Dec. 1998

    Article  Google Scholar 

  68. J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design. Boston, MA: Kluwer, 1998

    MATH  Google Scholar 

  69. I. Young, J. Greason, and K. Wong, “A PLL clock generator with 5 to 10MHz of clock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, pp. 1599–1607, Nov. 1992

    Article  Google Scholar 

  70. W. Rhee, “Design of high performance CMOS charge pumps in phase locked loop,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, May 1999, pp. 545–548

    Google Scholar 

  71. B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998

    Google Scholar 

  72. M. Johnson and E. Hudson, “A variable delay line PLL for CPU processor synchronization,” IEEE J. Solid-State Circuits, vol. 23, pp. 1218–1223, Oct. 1988

    Article  Google Scholar 

  73. A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, and D. Stiurca, “A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-µm CMOS PLL based on a sample-reset loop filter,” IEEE J. Solid-State Circuits, vol. 36, pp. 1673–1683, Nov. 2001

    Article  Google Scholar 

  74. J. Alvarez, H. Sanchez, and G. Gerosa, “A wide-band low-voltage PLL for PowerPC microprocessors,” IEEE J. Solid-State Circuits, vol. 30, pp. 383–391, Apr. 1995

    Article  Google Scholar 

  75. I. Novof, J. Austin, R. Kelkar, and S. Wyatt, “Fully integrated CMOS phase-locked loop with 15 to 240MHz locking range and +/−50 ps jitter,” IEEE J. Solid-State Circuits, vol. 30, pp. 1259–1266, Nov. 1995

    Article  Google Scholar 

  76. G. Chien, “Low-noise local oscillator design techniques using a DLL-based frequency multiplier for wireless applications,” Ph.D. dissertation, University of California at Berkeley, CA, Spring 2000

    Google Scholar 

  77. J. Lee, M. Kell, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronic Letters, vol. 36, pp. 1907–1908, Nov. 2000

    Article  Google Scholar 

  78. A. Lehner, R. Weigel, D. Sewald, and A. Hajimiri, “Design of a novel low-power 4th-order 1.7GHz CMOS frequency synthesizer for DCS-1800,” in Proc. IEEE ISCAS, vol. 5, Geneva, Switzerland, May 2000, pp. 637–640

    Google Scholar 

  79. R. Chang and L. Kuo, “A new low-voltage charge pump circuit for PLL,” in Proc. IEEE ISCAS, vol. 5, May 2000, pp. 701–704

    Google Scholar 

  80. J. Ingilo, “A 4GHz 40dB PSRR PLL for an SOC application,” in IEEE 1SSCC Dig. Tech. Papers, Feb. 2001, pp. 392–393, 469

    Google Scholar 

  81. J. Maneatis, “Low-jitter process independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–1732, Nov. 1996

    Article  Google Scholar 

  82. L. Wu, H. Chen, S. Nagavarapu, R. Geiger, E. Lee, and W. Black, “A monolithic l.25Gbits/sec CMOS clock recovery circuit for fiber channel transceiver,” in Proc. IEEE ISCAS, vol. 2, May 1999, pp. 565–568

    Google Scholar 

  83. L. Wu and W. Black, “A low jitter 1.25GHz CMOS analog PLL for clock recovery,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, June 1998, pp. 167–170

    Google Scholar 

  84. H. Djahanshali and C. Salama, “Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications,” in Proc. IEEE ISCAS, vol. 2, May 1999, pp. 93–96

    Google Scholar 

  85. D. Boerstler, “A low-jitter PLL clock generator for microprocessors with lock range of 340–612 MHz,” IEEE J. Solid-State Circuits, vol. 34, pp. 513–519, Apr. 1996

    Article  Google Scholar 

  86. K. Shu, E. Sánchez-Sinencio, F. Maloberti, and U. Eduri, “A comparative study of digital ΣΔ modulators for fractional-N synthesis,” in IEEE Proc. ICECS’01, Malta, Sept. 2001, pp. 1391–1394

    Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer Science+Business Media, Inc.

About this chapter

Cite this chapter

(2005). Other Building Blocks of PLL. In: CMOS PLL Synthesizers: Analysis and Design. The International Series in Engineering and Computer Science, vol 783. Springer, Boston, MA. https://doi.org/10.1007/0-387-23669-4_7

Download citation

  • DOI: https://doi.org/10.1007/0-387-23669-4_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-23668-1

  • Online ISBN: 978-0-387-23669-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation