Power Minimization Based on Best Primary Input Change Time

Summary

This chapter has described a technique for minimizing power dissipation in scan sequential circuits during test application. The BPIC test application strategy is equally applicable to minimizing power dissipation in partial scan sequential circuits. Since the test application strategy depends only on controlling primary input change time, power is minimized with no penalty in test area, performance, test efficiency, test application time or volume of test data. It is shown that combining the BPIC test application strategy and scan cell reordering using a simulated annealing-based design space exploration algorithm yields reductions in power dissipation during test application in partial scan sequential circuits.

This chapter has also shown that partial scan does not provide only the commonly known benefits such as lower test area overhead and test application time, but also lower power dissipation during test application and reduced computation time required for design space exploration, when compared to full scan. This reinforces that partial scan should be the preferred choice as design for test methodology for sequential circuits when low power dissipation during test application is of prime importance for high yield and reliability.