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CMOS Device Technology Trends for Power-Constrained Applications

  • Chapter
Power Aware Design Methodologies

Abstract

CMOS device technology has scaled rapidly for nearly three decades and has come to dominate the electronics world. Because of this scaling, CMOS circuits have become extremely dense, and power dissipation has become a major design consideration. Although industry projections call for at least another 10 years of progress, this progress will be difficult and is likely to be strongly constrained by power dissipation.

This chapter describes the present state of CMOS technology and the scaling principles that drive its progress. The physical effects that hinder this scaling are also examined in order to show how these effects interact with the practical constraints imposed by power dissipation. It is shown that scaling does not have a single end. Rather, each application has a different optimal end point that depends on its power dissipation requirements. A brief overview of some of the novel device options for extending the limits of scaling is also provided.

IBM T. J. Watson Research Center

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  1. David J. Frank
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Editors and Affiliations

  1. University of Southern California, USA

    Massoud Pedram

  2. University of California, Berkeley

    Jan M. Rabaey

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© 2002 Kluwer Academic Publishers

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Frank, D.J. (2002). CMOS Device Technology Trends for Power-Constrained Applications. In: Pedram, M., Rabaey, J.M. (eds) Power Aware Design Methodologies. Springer, Boston, MA. https://doi.org/10.1007/0-306-48139-1_2

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  • DOI: https://doi.org/10.1007/0-306-48139-1_2

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