Abstract
Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becomingmore and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this chapter, the opportunity for substantial power reduction by using hybrid reconfigurable processors will be explored. With the aid of an extensive example, it will be demonstrated that power reductions of orders of magnitude are attainable.
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Rabaey, J., Abnous, A., Zhang, H., Wan, M., George, V., Prabhu, V. (2002). Reconfigurable Processors — The Road to Flexible Power-Aware Computing. In: Pedram, M., Rabaey, J.M. (eds) Power Aware Design Methodologies. Springer, Boston, MA. https://doi.org/10.1007/0-306-48139-1_15
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DOI: https://doi.org/10.1007/0-306-48139-1_15
Publisher Name: Springer, Boston, MA
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