Abstract
This chapter describes the concept of dynamic power management (DPM), which is a methodology used to decrease the power consumption of a system. In DPM, a system is dynamically reconfigured to lower the power consumption while meeting some performance requirement. In other words, depending on the necessary performance and the actual computation load, the system or some of its blocks are tuned-off or their performance is lowered. This chapter reviews several approaches to system-level DPM, including fixed time-out, predictive shut-down or wake-up, and stochastic methods. In addition, it presents the key ideas behind circuit-level power management including clock gating, power gating and precomputation logic. The chapter concludes with a description of several runtime mechanisms for leakage power control in VLSI circuits.
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Fallah, F., Pedram, M. (2002). Circuit and System Level Power Management. In: Pedram, M., Rabaey, J.M. (eds) Power Aware Design Methodologies. Springer, Boston, MA. https://doi.org/10.1007/0-306-48139-1_13
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DOI: https://doi.org/10.1007/0-306-48139-1_13
Publisher Name: Springer, Boston, MA
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