Summary
This chapter has covered the basics in logic level modeling using the Verilog language. We have seen how to define gates and nets and interconnect them into more complex modules. The use of delays and strengths have been illustrated, and we have shown how module definitions can be parameterized.
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© 2002 Kluwer Academic Publishers
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(2002). Logic Level Modeling. In: The Verillog® Hardware Description Language. Springer, Boston, MA. https://doi.org/10.1007/0-306-47666-5_6
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DOI: https://doi.org/10.1007/0-306-47666-5_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7089-1
Online ISBN: 978-0-306-47666-2
eBook Packages: Springer Book Archive