Summary
To conclude, we have seen in detail how the 1149.1 architecture can be used to implement IC, board-level and system-level tests. There is more that can be done; this is the subject of the next chapter on advanced Boundary-Scan topics.
This chapter has highlighted some of the practical issues seen when attempting to do Boundary-Scan tests on real boards and systems. For example, the fanout of control cells to driver enables on-chip will interact with board-level interconnection topologies to create particular cases of faults that need special attention during test.
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© 2002 Kluwer Academic Publishers
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(2002). Boundary-Scan Testing. In: The Boundary-Scan Handbook. Springer, Boston, MA. https://doi.org/10.1007/0-306-47656-8_3
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DOI: https://doi.org/10.1007/0-306-47656-8_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-8277-5
Online ISBN: 978-0-306-47656-3
eBook Packages: Springer Book Archive