Synthesis and Verification of Finite State Machines

Summary

In this chapter we have discussed in detail the method due to Rho, et al, [228] for minimizing incompletely specified FSMs. This method is applicable in the most significant FSM synthesis scenario, in which the FSM is initially designed and simulated in some high level language, and then synthesized down to the RTL (Register Transfer Level) and logic levels of abstraction, which naturally leads to incomplete specification.

We further introduced an approach to FSM encoding that is used in the most widely available CAD tools. The basic notion is that of anticipating, in the encoding step, the the logic minimization operations that will likely be applied at later steps in the design cycle.

We concluded with a brief treatment of Hartmanis and Stearns’ elegant work on encoding via partitions with the substitution property.