Design for Test
DFT techniques are essential to an efficient and successful testing of the manufactured device.By implementing DFT features early in the design cycle,full test coverage on the design may be achieved,thereby reducing the debugging time normally spent at the tester after the device is fabricated. This chapter described the basic testability techniques that are currently in use,including a brief description of logic and memory BIST that is not yet supported by Synopsys.
A detailed description was provided for the scan insertion DFT technique, using the DFT Compiler.Various guidelines and solutions were also provided that may help the user to identify the issues and problems related to this technique.
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