Oversampling A/D Converters

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan
Part of the The International Series in Engineering and Computer Science book series (SECS, volume 543)


In this chapter we have discussed oversampling sigma-delta converters. They are suitable for high resolutions but the high oversampling ratio (OSR) limits the signal bandwidth. To increase the signal bandwidth cascaded modulators have been discussed. Gain errors in the integrators cause leakage of low order quantization noise at the output which limits the resolution of the converter. The integrator gain errors need not be as accurate as the full resolution and converters with up to 15 – 16 bit have been successfully implemented without calibration. To further reduce the quantization noise in the modulator a multi-bit quantizer can be used in the last stage of the converter. For a single stage modulator a multi-bit quantizer would require calibration since the DAC linearity directly limits linearity of the OSADC. For cascaded modulator however, the signal in the last stage has a weak correlation to the input signal and linearity errors in the multi-bit DAC will cause noise, not distortion. In addition to this the DAC linearity error is noise shaped, which significantly reduces the required linearity of the DAC. We have also discussed SC implementations of oversampled sigma-delta converters and investigated some of the most important limitations and how they affect the performance of the modulator. Based on the discussions and design example was presented.


Quantization Noise Slew Rate Signal Bandwidth Gain Error Parasitic Capacitor 
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© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Mikael Gustavsson
  • J. Jacob Wikner
  • Nianxiong Nick Tan

There are no affiliations available

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