Time-Interleaved A/D Converters
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In this chapter we have discussed the time-interleaved ADC. The performance is limited by mismatches between the channels. Gain and offset errors can be calibrated. A more severe problem is the phase skew errors which increases at high signal frequencies. The most effective way to reduce these errors is to use an input S/H circuit which usually needs an opamp that runs at the full speed of the ADC. The opamp is therefore difficult to design and power consuming. An improved global passive sampling technique that does not need an opamp was introduced. The limitations of the technique was also discussed. The phase skew distortion can be reduced by 10 to 20 dB compared to not using a global sampling technique.
KeywordsPassive Sampling Parasitic Capacitance Sampling Instant Clock Phase Gain Error
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- K. Y. Kim, N. Kusayanagi and A. A. Abidi, “A 10-b, 100-MS/s CMOS A/D Converter” IEEE J. of Solid-State Circuits, vol. 32, no. 6, pp. 302–11, Dec. 1997.Google Scholar
- H. Jin, E. Lee and M. Hassoun, “Time-Interleaved A/D Converter with Channel Randomization”, IEEE Intern. Symp. on Circuits and Systems, ISCAS-97, vol. 1, pp. 425–8, 1997.Google Scholar
- K. Dyer, D. Fu, P. Hurst and S. Lewis, “A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters” IEEE 1998 Intern. Symp. on Circuits and Systems, lSCAS-98, vol 1. pp. 13–16, 1998.Google Scholar
- S. R. Velazques, Hybrid Filter Banks for Analig/Digital Conversion, Ph.D. Thesis at Massachusetts Institute of Technology, June 1997.Google Scholar