Clock Jitter and Quantizer Metastability

Summary

Jitter which causes a variation in the width of the DAC pulses in a CT ΔΣM degrades modulator performance by whitening the in-band noise. Quantizer clock jitter and quantizer metastability are the two major mechanisms which cause this. We have derived one simple equation for each mechanism, (5.23) and (5.29), which allows estimation of maximum achievable performance. If building an integrated ΔΣM with an on-chip clock generated from a VCO, a properly-designed VCO should not cause a problematic level of jitter, though very high-resolution modulators or those with a center frequency away from dc might suffer. For quantizers, a three half-latch design is recommended for reducing adverse metastability effects over a simple master/slave design.Clocking faster than about 5% of f _T will limit performance to at most 12 bits in modulators with moderate OSRs. Higher resolutions can be obtained by oversampling more or clocking more slowly.