Principles of Verifiable RTL Design

Summary

In the early 1990s, the system design communities underwent tremendous productivity gains in gate-level design as engineers embraced synthesis technology. Unfortunately, this resulted in an increase in the design’s verification problem space for the design as well as the verification process. To keep up with escalating design complexity and sizes, we have presented a Verilog RTL coding style and a verifiable subset that facilitates optimizing the verification flow. We have emphasized the importance of two-state simulation, which we believe is fundamental to the RT level verification process--particularly at identifying start-up state initialization problems.

A verifiable RTL coding methodology permits the engineer to achieve greater verification coverage in minimal time, enhances cooperation and support for multiple EDA tools within the flow, clarifies RTL design intent, and facilitates emerging verification processes. The design project will accomplish a reduction in development time-to-market while simultaneously achieving a higher level of verification confidence in the final product through the adoption a Verifiable RTL design methodology.