Summary
In this chapter, we addressed the problem of complexity due to competing tool coding requirements by: (a) introducing a simplified and tool efficient Verilog RTL verifiable subset, (b) introducing an Object-Oriented Hardware Design (OOHD) methodology, (c) detailing a linting methodology used to enforce project specific coding rules and tool performance checks.
By constraining the RTL to a verifiable subset, the designer will succeed in augmenting their traditional verification process with cycle-based simulation, 2-state simulation, formal equivalence checking, and model checking. A verifiable RTL coding style allows the engineer to achieves greater verification coverage in minimal time, enhances the cooperation and support for multiple EDA tools within the flow, clarifies RTL design intent, and facilitates emerging verification processes.
By applying the principle of information hiding and developing an OOHD methodology, the designer will succeed in isolating design details within tool-specific libraries. This methodology facilitates simultaneously optimizing the performance of simulation, equivalence checking, model checking and physical design within a project’s design flow. Furthermore, an OOHD methodology allows adding new features and tools to the design flow throughout the duration of a project, without interfering with the text or functional intent of the original design.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Rights and permissions
Copyright information
© 2002 Kluwer Academic Publishers
About this chapter
Cite this chapter
(2002). RTL Methodology Basics. In: Principles of Verifiable RTL Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-47016-0_3
Download citation
DOI: https://doi.org/10.1007/0-306-47016-0_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7788-7
Online ISBN: 978-0-306-47016-5
eBook Packages: Springer Book Archive