The Verification Process

Summary

In this chapter, we examined various components of the verification process specifically related to verifiable RTL design-such as design specification, test strategies, coverage analysis, event monitoring and assertion checking. Furthermore, this chapter introduced four essential principles of verifiable RTL design. We emphasized the importance of specification in the verification process, which we referred to as the Fundamental Verification Principle. This principle enables us to reduce design complexity while increasing verifiability. We then introduced the Retain Useful Information Principle, which enables us to globally optimize processes within the design flow while capturing environmental assumptions and design knowledge. Next, we discussed the importance of maintaining a clear separation of verification concerns, which provides the foundation for today’s static verification design methodology. We refer to this as the Orthogonal Verification Principle. Finally, we introduced the Functional Observation Principle that is fundamental to the verification process’ ability to observe (white-box testing) and measure (coverage) functional behavior.

In addition to the principles presented in this chapter, a simple and effective coding technique for embedding event monitors and assertion checkers directly into the RTL was our main focus. This coding technique provides a mechanism for (a) measuring functional coverage, (b) increasing verification observability, and (c) defining verification targets for block-level simulation and model checking.