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Data Storage, Input, and Output

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Introduction to Parallel Processing

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References and Suggested Reading

  1. Burger, D., S. Kaxiras, and J. R. Goodman, “Data Scalar Architectures,” Proc. Int’l. Symp. Computer Architecture, June 1997, pp. 338–349.

    Google Scholar 

  2. Chen, P. M., E. K. Lee, G. A. Gibson, R. H. Katz, and D.A. Patterson, “RAID: High-Performance, Reliable Secondary Storage,” ACM Computing Surveys, Vol. 26, No. 2, pp. 145–185, June 1994.

    Article  ISI  Google Scholar 

  3. Chen, S., and D. Towsley, “A Performance Evaluation of RAID Architectures,” IEEE Trans. Computers, Vol. 45, No. 10, pp. 1116–1130, October 1996.

    Google Scholar 

  4. Friedman, M. B., “RAID Keeps Going and Going and ...,” IEEE Spectrum, Vol. 33, No. 4, pp. 73–79, April 1996.

    Article  ISI  Google Scholar 

  5. Ganger, G. R., B. R. Worthington, R. Y. Hou, and Y. N. Patt, “Disk Arrays: High-Performance, High-Reliability Storage Subsystems,” IEEE Computer, Vol. 27, No. 3, pp. 30–36, March 1994.

    Google Scholar 

  6. Hirata, H., et al., “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads,” Proc. 19th Int. Symp. Computer Architecture, pp. 136–145, May 1992.

    Google Scholar 

  7. Parhami, B., “A Highly Parallel Computing System for Information Retrieval,” AFIPS Conf. Proc., Vol. 41 (1972 Fall Joint Computer Conf.), AFIPS Press, pp. 681–690.

    Google Scholar 

  8. Patterson, D. A., and J. L. Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, 1996.

    Google Scholar 

  9. Thakur, R., A. Choudhary, R. Bordawekar, S. More, and S. Kuditipudi, ‘Passion: Optimized I/O for Parallel Applications,” IEEE Computer, Vol. 29, pp. 70–78, June 1996.

    Google Scholar 

  10. Tolmie, D., “High Performance Parallel lnterface (HIPPI),” in High Performance Networks—Technology and Protocols, edited by A. Tantawy, Kluwer, 1994, pp. 131–156.

    Google Scholar 

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© 2002 Kluwer Academic Publishers

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(2002). Data Storage, Input, and Output. In: Introduction to Parallel Processing. Series in Computer Science. Springer, Boston, MA. https://doi.org/10.1007/0-306-46964-2_18

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  • DOI: https://doi.org/10.1007/0-306-46964-2_18

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-306-45970-2

  • Online ISBN: 978-0-306-46964-0

  • eBook Packages: Springer Book Archive

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