FPGA implementation of modular exponentiation

  • Alexander Tiountchik
  • Elena Trichina
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1586)


An efficient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs. One XC6000 chip, or 4 Kgates accommodates 132-bit long integers. 16 Kgates is required for modular exponentiation of 512 bit keys, with the estimated bit rate 800 Kb/sec.


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Copyright information

© Springer-Verlag 1999

Authors and Affiliations

  • Alexander Tiountchik
    • 1
  • Elena Trichina
    • 2
  1. 1.Institute of MathematicsNational Academy of Sciences of BelarusMinskBelarus
  2. 2.Advanced Computing Research CentreUniversity of South AustraliaMawson LakesAustralia

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