MorphoSys: a reconfigurable processor targeted to high performance image application

  • Guangming Lu
  • Ming-hau Lee
  • Hartej Singh
  • Nader Bagherzadeh
  • Fadi J. Kurdahi
  • Eliseu M. Filho
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1586)

Abstract

This paper addresses the design idea of the MorphoSys Reconfigurable processor developed by the researchers in the UC, Irvine. With the demand to perform the multimedia operations efficiently, it is one of the directions that general processor needs to incorporate with some reconfigurable computing units, like FPGA. In MorphoSys project, we successfully propose a prototype to fulfill the above trend, which is comprised of a simplified general purpose MIPS-like RISC processor, called TinyRISC and 8×8 coarse grained reconfigurable cells, organized as SIMD architecture. MorphoSys is realized using 0.35um technology, and runs at 100Mhz with impressive performance enhancement compared with other architectures.

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Copyright information

© Springer-Verlag 1999

Authors and Affiliations

  • Guangming Lu
    • 1
  • Ming-hau Lee
    • 1
  • Hartej Singh
    • 1
  • Nader Bagherzadeh
    • 1
  • Fadi J. Kurdahi
    • 1
  • Eliseu M. Filho
    • 2
  1. 1.Department of Electrical and Computer EngineeringUniversity of CaliforniaIrvineUSA
  2. 2.Department of Systems and Computer EngineeringFederal University of Rio de JaneiroRio de JaneiroBrazil

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