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Integrated block-processing and design-space exploration in temporal partitioning for RTR architectures

  • Meenakshi Kaul
  • Ranga Vemuri
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1586)

Abstract

We present an automated temporal partitioning and design space exploration methodology that temporally partitions behavior specifications. We propose block-processing in the temporal partitioning framework for reducing the reconfiguration overhead for partitioned designs. Block-processing is a technique used traditionally in the area of parallel compilers, for increasing the computation speed by processing several inputs simultaneously. Block-processing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. An ILP-based methodology has been proposed to solve this problem. We present experimental results for the Discrete Cosine Transform (DCT).

Keywords

Execution Time Discrete Cosine Transform Design Point Task Graph Design Space Exploration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag 1999

Authors and Affiliations

  • Meenakshi Kaul
    • 1
  • Ranga Vemuri
    • 1
  1. 1.Department of ECECSUniversity of CincinnatiCincinnati0030

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