Load balancing in parallel circuit testing with annealing-based and genetic algorithms

  • C. Gil
  • J. Ortega
  • A. F. Díaz
  • M. G. Montoya
  • A. Prieto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1498)


A new combination of Simulated Annealing and Tabu Search is presented for load balancing in a parallel circuit testing procedure. The testing procedure requires a circuit partitioning algorithm to distribute the workload among the processors in such a way that similar sized parts of the circuit are assigned to each processor while communications are minimised. The hybrid algorithm for circuit partitioning is compared with pure tabu search and simulated annealing algorithms, and also with a genetic algorithm. The solutions obtained are evaluated for the circuits of a frequently used benchmark set.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Aarts, E., Korst, J.: Simulated Annealing and Boltzmann Machines. A stochastic Approach to Combinatorial Optimization and Neural Computing. John Wiley & Sons, 1990.Google Scholar
  2. 2.
    Alpert, C.J., Kahng, A.: Recent Developments in Netlist Partitioning: A survey. Integration: the VLSI Journal, 19 (2) (1995) 1–81.zbMATHCrossRefGoogle Scholar
  3. 3.
    Brglez, F., Fujiwara, H.: Neural Netlist of Ten Combinational Benchmark Circuts and a Target Translator in FORTRAN. In: Proceedings of IEEE Int. Symp. Circuits Syst., Special Session ATPG, (1985).Google Scholar
  4. 4.
    Garey, M.R., Johnson, D.S.: Computers and Interactibility: A Guide to the Theory of NP-Completeness. W.H. Freeman & Company, San Francisco (1979).Google Scholar
  5. 5.
    Gil, C., Ortega, J.: A Parallel Test Pattern Generator based on Spectral Techniques. In: Proceedings of the 5th Euromicro on PDP, London, UK (January 22–24, 1997). IEEE Computer Society, (1997) 199–204.Google Scholar
  6. 6.
    Gil, C., Ortega, J.: Parallel Test Generation using circuit partitioning and spectral techniques. In: Proceedings of the 6th Euromicro Workshop on PDP, Madrid, Spain (January 21–23, 1998). IEEE Computer Society (1998) 264–270.Google Scholar
  7. 7.
    Gil, C., Ortega, J.: Algebraic Test-Pattern Generation based on the Reed-Muller Spectrum. IEE Proc. Computer and Digital Techniques (accepted for publication July 1998).Google Scholar
  8. 8.
    Glover, F., Laguna, M.: Tabu Search. In: Modern Heuristic Techniques for Combinatorial Problems. C.R. Reeves (Eds.). Blackwell, London (1993) 70–150.Google Scholar
  9. 9.
    Goldberg, D.E.: Genetic Algorithms in Search, Optimization, and Machine Learning, Addison-Wesley (1989).Google Scholar
  10. 10.
    Green, D.H.: Families of Reed-Muller forms Int. J. Electronics. 70 (2) (1991) 259–280.zbMATHGoogle Scholar
  11. 11.
    Klenke, R.H., Williams R.D., Aylor, J.H.: Parallel-Processing Techniques for Automatic Test Pattern Generation. IEEE Computer, (January 1992), 71–84.Google Scholar
  12. 12.
    Klenke, R. H., Williams, R. D., Aylor, J. H.: Parallelization Methods for Circuit Partitioning Based Parallel Automatic Test Pattern Generation. IEEE VLSI Test Symposium, (1993) 71–78.Google Scholar
  13. 13.
    Kumar, V., Grama, A., Gupta, A., Karypis, G.: Introduction to Parallel Computing. Design and analysis of algorithms. The Benjamin/Cummings Publishing company (1994).Google Scholar
  14. 14.
    Goldberg, D.E.: Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley (1989).Google Scholar
  15. 15.
    Patil, S., Banerjee, P.: A Parallel Branch and Bound Algorithm for Test Generation. IEEE Trans. on CAD. (March 1990) 9 (3) (1990) 313–322.Google Scholar
  16. 16.
    Patil, S., Banerjee, P., Polychronopoulos, C.D.: Efficient circuit partitioning algorithms for parallel logic simulation. In: Proceeding of the Supercomputing Conference (1989).Google Scholar
  17. 17.
    Reeves, C.R.: Genetic Algorithms. In: Modern Heuristic Techniques for Combinatorial Problems. C.R. Reeves (Eds.) Blackwell (1993) 151–196.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • C. Gil
    • 1
  • J. Ortega
    • 2
  • A. F. Díaz
    • 2
  • M. G. Montoya
    • 1
  • A. Prieto
    • 2
  1. 1.Dept. de Arquitectura de Computadores y ElectrónicaUniv. AlmeríaSpain
  2. 2.Dept. de Arquitectura y Tecnología de ComputadoresUniv. GranadaSpain

Personalised recommendations