XILINX4000 architecture — Driven synthesis for speed

  • I. Lemberski
  • M. Ratniece
Miscellaneous
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)

Abstract

Architecture-driven (instead of LUT-driven) method of boolean functions logic synthesis for speed is proposed. It takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each node can be mapped onto 4 input LUT). In the second step, selected 4 fanin nodes within a critical path are re-decomposed into 3 fanin nodes to ensure mapping onto 3 input LUTs. Re-decomposition task is formulated as substituting node two fanins for exactly one fanin. Either existing node or one especially created, is considered as a fanin to be substituted for. The extended PLA format describing a multi-level boolean network, is proposed. Based on this description, substituting is formulated in terms of a covering task.

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References

  1. 1.
    Cong, J, Ding, Y.: Combinational Logic Synthesis for LUT Based Field Programmable Gate arrays. ACM Trans. on Design Automation of Electronic Systems, Vol.1, No. 2, April (1996) 145–204CrossRefGoogle Scholar
  2. 2.
    Abouzeid, P., Babba, B., Crastes de Paulet, M., Saucier, G.: Input-Driven Partitioning Methods and Application to Synthesis on Table-Look-up-Based FPGA's. IEEE Trans. CAD, Vol. 12, No. 7, July (1993) 913–925Google Scholar
  3. 3.
    Murgai, R., Brayton, R., Sangiovanni-Vincentelli, A.:Logic Synthesis for Field-Programmable Gate Arrays. Kluwer Academic Publishers (1995)Google Scholar
  4. 4.
    Sentovich, E. et al: SIS: a System for Sequential Circuit Synthesis. Electronic Research Laboratory Memorandum No. UCB/ERL M92/41(1992)Google Scholar
  5. 5.
    Grass, W., Lemberski, I.: Support-Based State Encoding targeting FSM Optimal LUT FPGA Implementation.-Int.Workshop on Logic and Architecture Synthesis, Grenoble, France (1997) 97–104Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • I. Lemberski
    • 1
  • M. Ratniece
    • 1
  1. 1.Riga Aviation UniversityRigaLatvia

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