Implementing processor arrays on FPGAs

  • István Vassányi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


Fine grain FPGAs offer a suitable medium for the implementation of bit level processor arrays. This paper describes a layout method, and a parametrized tool based on it, for designing two-dimensional array structures on FPGAs. The use of the tool is demonstrated by an example application in morphological image processing. The tool observes highlevel array structure, and thus it can find better layouts for arrays on the XC6216 FPGA, than the tool of the FPGA vendor (XACT 6000). Additionally, non-rectangular (distorted) layouts were found to perform better than rectangular ones.


Critical Path Array Structure Processor Array Good Layout Morphological Image Processing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • István Vassányi
    • 1
  1. 1.Department of Information SystemsUniversity of VeszprémHungary

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