High speed low level image processing on FPGAs using distributed arithmetic

  • Elena Cerro-Prada
  • Philip B. James-Roxby
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


A method of calculating the 3x3 mask convolution required for many low level image processing algorithms is presented, which is well suited for implementing on reconfigurable FPGAs. The approach is based on distributed arithmetic, and uses the symmetry of weights present in many filter masks to save on circuit space, at the expense of requiring custom circuitry for each set of coefficients. A four product example system has been implemented on a Xilinx XC6216 device to demonstrate the suitability of this reconfigurable architecture for image processing systems.


Expense Convolution 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Jaggernauth, J., Loui, A.C.P., Venetsanopoulos, A.N.: “Real-Time Image Processing by Distributed Arithmetic Implementation of Two-Dimensional Digital Filters”, IEEE Trans. ASSP, Vol. ASSP-33, No. 6, pp. 1546–155, Dec. 1985CrossRefGoogle Scholar
  2. 2.
    Goslin, G.R.: “Using Xilinx FPGAs to design custom digital signal processing devices”, available at http://www.xilinx.com/appnotes/dspx5dev.htmGoogle Scholar
  3. 3.
    Mintzer, L.:”FIR Filters with Field-Programmable Gate Arrays”, Journal of VLSI Signal Processing, Vol. 6, pp.119–127, 1993CrossRefGoogle Scholar
  4. 4.
    Xilinx Inc., “XC6200 field programmable gate arrays”, available at http://www.xilinx.com/partinfo/6200.pdfGoogle Scholar
  5. 5.
    Xilinx Inc., “A fast constant coefficient multiplier for the XC6200”, available at http://www.xilinx.com/xapp/xapp082.pdfGoogle Scholar
  6. 6.
    Duncan, A., Kean, T: “DES keybreaking, encryption and decryption on the XC6216”, Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998Google Scholar
  7. 7.
    Wirth, N.: “Digital circuit design”, Springer-Verlag Berlin Heidelberg, 1995MATHGoogle Scholar
  8. 8.
    Singh, S, Slous, R.: “Accelerating Adobe Photoshop with reconfigurable logic” Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998Google Scholar
  9. 9.
    Hauck, S, Z. Li, Schwabe, E.: “Configuration compression for the Xilinx XC6200 FPGA” Proc. 6th Annual IEEE Symposium on Custom Computing Machines, 1998Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Elena Cerro-Prada
    • 1
  • Philip B. James-Roxby
    • 2
  1. 1.Digital Systems and Vision Processing GroupThe University of BirminghamBirminghamUK
  2. 2.School of Electronic and Electrical EngineeringThe University of BirminghamBirminghamUK

Personalised recommendations