A high-performance computing module for a low earth orbit satellite using reconfigurable logic

  • Neil W. Bergmann
  • Peter R. Sutton
Miscellaneous
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)

Abstract

A hierarchy of FPGAs, DSPs, and a multiprocessing microprocessor provide a layered high performance computing module which will be used to enhance the performance of a low-earth orbit satellite, FedSat-1, which will be operational in 2001. The high performance computer will provide additional hardware redundancy, on-board data processing, data filtering and data compression for science data, as well as allowing experiments in dynamic reconfigurability of satellite computing hardware in space.

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References

  1. 1.
    Kingwell, J., Embleton, B.: Cooperative Research Centre for Satellite Systems, World Wide Web page at http://www.crcss.csiro.au/, (1998)Google Scholar
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    Jilla, C. D., Miller, D. W.: Satellite Design: Past, Present and Future, International Journal of Small Satellite Engineering, Vol. 1, No. 1, (1995) World Wide Web page at http://www.ee.surrey.ac.uk/EE/CSER/UOSAT/IJSSE/issue1/cjilla/cjilla.html Google Scholar
  3. 3.
    Wagner, D.J.: Spaceborne Processors: Past, Present and Future Satellite Onboard Computers, Proceedings of 49th International Astronautical Federation Congress, Melbourne (1998)Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Neil W. Bergmann
    • 1
  • Peter R. Sutton
    • 1
  1. 1.Cooperative Research Centre for Satellite SystemsQueensland University of TechnologyBrisbaneAustralia

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