Increasing microprocessor performance with tightly-coupled reconfigurable logic arrays

  • Sergej Sawitzki
  • Achim Gratz
  • Rainer G. Spallek
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


Conventional approaches to increase the performance of microprocessors often do not provide the performance boost one has hoped for due to diminishing returns. We propose the extension of a conventional hardwired microprocessor with a reconfigurable logic array, integrating both conventional and reconfigurable logic on the same die. Simulations have shown that even a comparatively simple and compact extension allows performance gains of 2–4 times over conventional RISC processors of comparable complexity, making this approach especially interesting for embedded microprocessors.


Cache Size Partial Configuration FPGA Board Compact Extension Reconfigurable Logic 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Sergej Sawitzki
    • 1
  • Achim Gratz
    • 1
  • Rainer G. Spallek
    • 1
  1. 1.Institute of Computer Engineering Faculty of Computer ScienceDresden University of TechnologyDresdenGermany

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