Increasing microprocessor performance with tightly-coupled reconfigurable logic arrays

  • Sergej Sawitzki
  • Achim Gratz
  • Rainer G. Spallek
Miscellaneous
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)

Abstract

Conventional approaches to increase the performance of microprocessors often do not provide the performance boost one has hoped for due to diminishing returns. We propose the extension of a conventional hardwired microprocessor with a reconfigurable logic array, integrating both conventional and reconfigurable logic on the same die. Simulations have shown that even a comparatively simple and compact extension allows performance gains of 2–4 times over conventional RISC processors of comparable complexity, making this approach especially interesting for embedded microprocessors.

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References

  1. 1.
    Hennessy, J.L., Patterson, D.A.: Computer Architecture — A Quantitative Approach. Second Edition. Morgan Kaufmann Publishers, Inc. (1996)Google Scholar
  2. 2.
    Patterson, D.A. Anderson, T. et.al.: A Case for Intelligent RAM. IEEE Micro, 17(2):34–44 (March/April 1997)CrossRefGoogle Scholar
  3. 3.
    Essen, A., Goldstein, S.: Performance Evaluation of the Superscalar Speculative Execution HaL SPARC64 Processor, in Proceedings of Hot Chips VII, p.3.1 (August 1995)Google Scholar
  4. 4.
    Miyajima, H., Inoue, K. et.al.: On-Chip Memorypath Architectures for Parallel Processing RAM (PPRAM). Technical Report PPRAM-TR-17, Department of Computer Science and Communication Engineering, Kyushu University (May 1997)Google Scholar
  5. 5.
    Ast, A., Hartenstein, R. et.al.: Novel High Performance Machine Paradigms and Fast Turnaround ASIC Design Methods: A Consequence of and a Challenge to Field-Programmable Logic, in Field Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Vol. 705 of Lecture Notes in Computer Science, pp. 210–217, Springer-Verlag (1993)Google Scholar
  6. 6.
    Halverson Jr., R., Lew, A.: An FPGA-Based Minimal Instruction Set Computer. Technical Report ICS-TR-94-28, Information and Computer Sciences Department, University of Hawaii at Manoa (January 1995)Google Scholar
  7. 7.
    Wittig, R., Chow, P.: OneChip: An FPGA Processor With Reconfigurable Logic, in Proceedings of FCCM'96, pp. 126–135 (April 1996)Google Scholar
  8. 8.
    Hauser, J.R., Wawrzynek, J.: Garp: A MIPS Processor with a Reconfigurable Coprocessor, in Proceedings of FCCM'97, pp. 24–33 (April 1997)Google Scholar
  9. 9.
    National Semiconductor Corporation: NAPA 1000 Adaptive Processor. http://www.national.com/appinfo/milaero/napa1000/index.htmlGoogle Scholar
  10. 10.
    Razdan, R.: PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, Cambridge, Massachusetts (1994)Google Scholar
  11. 11.
    Lee, R.B.: Accelerating Multimedia with Enhanced Microprocessors. IEEE Micro, 15(2):22–32 (April 1995)CrossRefGoogle Scholar
  12. 12.
    Gehring, S.W., Ludwig, S.: The Trianus System and its Application to Custom Computing, in Proceedings of FPL'96 (September 1996)Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Sergej Sawitzki
    • 1
  • Achim Gratz
    • 1
  • Rainer G. Spallek
    • 1
  1. 1.Institute of Computer Engineering Faculty of Computer ScienceDresden University of TechnologyDresdenGermany

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