A field-programmable gate-array system for evolutionary computation
In evolutionary computation, evolutionary operations are applied to a large number of individuals (genes) repeatedly. The computation can be pipelined (evolutionary operators) and parallelized (a large number of individuals) by dedicated hardwares, and high performance are expected. However, details of the operators depend on given problems and vary considerably. Systems with field programmable gate arrays can be reconfigured and realize the most suitable circuits for given problems. In this paper, we show that a hardware system with two FPGAs and SRAMs can achieve 50∼130 times of speedup compared with a workstation (200MHz) in some evolutionary computation problems. With a larger system, we believe that we can realize more than 10 thousands of speedup.
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- 1.S. D. Scott, A. Samal and S Seth, “HGA: A Hardware-Based Genetic Algorithm”, Int. Symposium on Field-Programmable Gate Array, 1995, pp.53–59.Google Scholar
- 2.P. Graham and B. Nelson, “Genetic Algorithm In Software and In Hardware — A Performance Analysis of Workstation and Custom Computing Machine Implementations”, FPGAs for Custom Computing Machines, 1996 pp.216–225.Google Scholar
- 3.D.E. Goldberg, “Genetic Algorithms in Search, Optimization and Machine Learning”, Addison-Wesley, 1989.Google Scholar
- 4.D. A. Buell, J.M. Arnold and W.J. Klenfelder, “Splash2: FPGAs in a Custom Computing Machine”, IEEE Computer Society Press, 1996.Google Scholar
- 5.D.E. Goldberg, and K. Deb, “A Comparative Analysis of Selection Schemes Used in Genetic Algorithms” 1991, pp.69–93Google Scholar
- 6.V.S. Gordon and D. Whitley, “Serial and Parallel Genetic Algorithms as Function Optimizer”, Fifth International Conference on Genetic Algorithms 1993 pp177–190.Google Scholar
- 7.K. Lindgren, “Evolutionary Phenomena in Simple Dynamics”, Artificial Life II, pp.295–312, 1991.Google Scholar