Dynamic specialisation of XC6200 FPGAs by partial evaluation
This paper describes preliminary results of dynamically specialising Xilinx XC6200 FPGA circuits using partial evaluation. This method provides a systematic way to manage the complexity of dynamic reconfiguration in the special case where a general circuit is specialised with respect to a slowly changing input. We describe how we address the verification and run-time support issues which are raised when one modifies a circuit at run-time.
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