High-level synthesis for dynamically reconfigurable hardware/software systems

  • Rainer Kress
  • Andreas Pyttel
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


Dynamically reconfigurable hardware/software systems allow a flexible adaptation of their hardware part to the necessities of the application by reprogramming it at run-time. Traditional design methodologies do not support dynamic hardware structures efficiently. Thus the design space is not exploited thoroughly and the application might not be adequately implemented. In this paper we concentrate on the high-level synthesis of the hardware part including temporal partitioning to effectively use the dynamic nature of the target FPGA circuits.


  1. 1.
    J. Fleischmann, K. Buchenrieder, R. Kress: A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems; 6th International Workshop on Hardware/Software Codesign, CODES/CASHE'98, Seattle, March 1998Google Scholar
  2. 2.
    M. Kaul, R. Vemuri: Optimal Temporal Partitioning for Reconfigurable Architectures; Design Automation and Test Conference in Europe, DATE'98, Paris, Feb. 1998Google Scholar
  3. 3.
    Y.-L. Lin: Recent Developments in High-Level Synthesis; ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 1, Jan. 1997Google Scholar
  4. 4.
    P. Lysaght, G. McGregor, J. Stockwood: Configuration Controller Synthesis for Dynamically Reconfigurable Systems; IEE Colloquium on Hardware/Software Cosynthesis for Reconfigurable Systems, HP Labs., Bristol, UK, Feb. 1998Google Scholar
  5. 5.
    W. Luk, N. Shirazi, S. R. Guo, P. Y. K. Cheung: Pipeline Morphing and Virtual Pipelines; in W. Luk, P. Y. K. Cheung, M. Glesner (Eds.):Field-Programmable Logic and Applications, Lecture Notes in Computer Science 1304, Sept. 1997Google Scholar
  6. 6.
    A. Pyttel, A. Sedlmeier: HW/SW Systems Prototyping with Statically and Dynamically Reconfigurable FPGAs; Design Automation and Test Conference in Europe, DATE'98, Designer Track, Paris, Feb. 1998Google Scholar
  7. 7.
    M. Vasilko: Bournemouth University Page of Dynamically Reconfigurable Hardware; http://dec.bournemouth.ac.uk/dec_ind/decind6/drhw_page.html, Jan. 1997Google Scholar
  8. 8.
    M. Vasilko, D. Ait-Boudadoud: Architectural Synthesis Techniques for Dynamically Reconfigurable Logic; in Hartenstein, Glesner (Eds.): Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, Lecture Notes in Computer Science 1142, Sept. 1996Google Scholar
  9. 9.
    N. N.: The Programmable Logic Data Book; Xilinx Inc., San José, CA, 1996Google Scholar
  10. 10.
    N. N.: A Fast Constant Coefficient Multiplier for the XC6200; Xilinx Application Note XAPP 082, Xilinx Inc., San José, CA, Aug. 1997Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Rainer Kress
    • 1
  • Andreas Pyttel
    • 1
  1. 1.Corporate TechnologySiemens AGMunichGermany

Personalised recommendations