Instruction-level parallelism for reconfigurable computing

  • Timothy J. Callahan
  • John Wawrzynek
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language.


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Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Timothy J. Callahan
    • 1
  • John Wawrzynek
    • 1
  1. 1.University of California at BerkeleyBerkeleyUSA

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