Exploiting contemporary memory techniques in reconfigurable accelerators

  • R. W. Hartenstein
  • M. Herz
  • T. Hoffmann
  • U. Nageldinger
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The memory employs DRAMs instead of the more expensive SRAMs. To enhance the memory bandwidth, we use a threefold approach: modern memory devices featuring burst mode, an efficient memory architecture with multiple parallel modules, and memory access optimization for single applications. To exploit the features of the memory architecture, we introduce a strategy to determine optimized storage schemes for a class of applications.


Memory Access Memory Bandwidth Execution Model Data Memory Memory Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    R.W. Hartenstein, J. Becker, R. Kress: Custom Computing Machines vs. Hardware/Software Co-Design: From a Globalized point of view; Proc. of the 6th Intl. Workshop of Field Programmable Logic and Applications FPL'96, pp. 65–76, Springer LNCS, 1996.Google Scholar
  2. 2.
    W.H. Mangione-Smith, et. al.: Seeking Solutions in Configurable Computing; IEEE Computer, Dec. 1997.Google Scholar
  3. 3.
    D.A. Patterson, J.L. Hennessy: Computer Architecture, A Quantitative Approach; Morgan Kaufmann Publishers, 1990.Google Scholar
  4. 4.
    P. Budnik, D.J. Kuck: The Organization and Use of parallel Memories; IEEE Transactions on Computers, Dec. 1971.Google Scholar
  5. 5.
    K. Kim, V.K. Prasanna: Perfect Latin Squares and Parallel Array Access; Proc. Int. Symposium on Computer Architecture, ACM Press, 1989.Google Scholar
  6. 6.
    A. Deb: Multiskewing — A Novel Technique for Optimal Parallel Memory Access; IEEE Transactions on Parallel and Distributed Systems; Vol. 7, No. 6, June 1996.Google Scholar
  7. 7.
    M.E. Wolf, M.S. Lam: A Data Locality Optimizing Algorithm; Proc. of the SIGPLAN'91 Conf. on Programming Language Design and Implementation, pp. 30–44, Toronto, Canada, June 1991.Google Scholar
  8. 8.
    J. M. Anderson, S. P. Amarasinghe and M. S. Lam: Data and computation transformations for multiprocessors; Proceedings of the Fifth ACM SIGPLAN Symp. on Principles and Practice of Parallel Processing, July 1995.Google Scholar
  9. 9.
    R.W. Hartenstein, J. Becker, M. Herz, U. Nageldinger: A Novel Universal Sequencer Hardware; Proceedings of Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 8–11, 1997.Google Scholar
  10. 10.
    R.W. Hartenstein,A. Hirschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7 91/92, p. 181–198, North Holland.Google Scholar
  11. 11.
    N.N.: Siemens Multibank DRAM; Ultra-high performance for graphic applications; Siemens Semiconductor Group, Oct. 1996.Google Scholar
  12. 12.
    R.W. Hartenstein, J. Becker, R. Kress, H. Reinig: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996.Google Scholar
  13. 13.
    R. Kress: A Fast Reconfigurable ALU for Xputers; Ph.D. dissertation, University of Kaiserslautem, 1996.Google Scholar
  14. 14.
    J. Becker: A Partitioning Compiler for Computers with Xputer-based Accelerators; Ph.D. dissertation, University of Kaiserslautern, 1997.Google Scholar
  15. 15.
    K. Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers; Ph.D. dissertation, University of Kaiserslautern, 1994.Google Scholar
  16. 16.
    R. W. Hartenstein, R. Kress: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Asia and South Pacific Design Automation Conference, ASP-DAC95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug. 29–Sept. 1, 1995.Google Scholar
  17. 17.
    N.N: The Burst EDO DRAM Advantage, Technical Note TN-04-41, Micron Technology Inc., 1995Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • R. W. Hartenstein
    • 1
  • M. Herz
    • 1
  • T. Hoffmann
    • 1
  • U. Nageldinger
    • 1
  1. 1.University of KaiserslauternKaiserslauternGermany

Personalised recommendations