Prototyping new ILP architectures using FPGAs

  • Joy Shetler
  • Brian Hemme
  • Chia Yang
  • Christopher Hinsz
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


We are developing a set of custom computer applications coupled with FPGAs and other physical hardware that can be used to emulate an entire processor with monitor functions. This environment provides a working processor research platform complete with operational software that will allow productive computer architecture research to be conducted at both the upper division undergraduate level and at the graduate theses level. The focus of the research component is to devise and test Instruction Level Parallelism (ILP) techniques and mechanisms. The rapid-prototyping platform developed for this effort can be used for several upper division computer architecture and microprocessor courses. The ideas we develop are to be incorporated into the microprocessor and computer architecture curriculum. To implement this system, we have developed a set of VHDL modules to allow for control and monitoring of the processor, a basic operating system with a set of test applications, and a reconfigurable assembler as well as utility and interface applications.


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  1. 1.
    Altera, 1996 Data Book. San Jose, Altera, 1996Google Scholar
  2. 2.
    Berkeley Reconfigurable Architecture, Systems and Software Group. http://HTTP.CS.Berkeley.EDU/Research/Projects/brass/Google Scholar
  3. 3.
    Don Bouldin, “Report of the 1993 Workshop on Rapid Prototyping of Microelectronic Systems for Universities”, Computer Architecture News, June 1994, pp. 19–26Google Scholar
  4. 4.
    BYU Electrical Engineering's Configurable Computing Laboratory. Scholar
  5. 5.
    Christian Iseli and Eduardo Sanchez, “Spyder: A Reconfigurable VLIW Processor using FPGAs”, Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, April 1993, pp. 17–24Google Scholar
  6. 6.
    Hemme, Brian. “An Expandable Computer Architecture Research Platform” Thesis California Polytechnic State University, San Luis Obispo, CA 1998.Google Scholar
  7. 7.
    J. L. Hennessy and D. A. Patterson, “Computer Architecture — A quantitative Approach.” 2nd Edition, Morgan Kaufmann Publishers, Inc., 1995.Google Scholar
  8. 8.
    Reconfigurable Architecture Group at Glasgow Scotland. Scholar
  9. 9.
    J. Shetler and S. Butner, “Multiple Stream Execution on the DART Processor”, 1991 Int.Conf. on Parallel Processing, August 1991, pp. I92–I96Google Scholar
  10. 10.
    Joy Shetler, “Mentoring Graduate and Undergraduate Students in Microelectronic Systems Architecture Education and Research”, 1997 ASEE/IEEE Frontiers in Engineering Conference Proceedings, Session F2B.4, CD-ROMGoogle Scholar
  11. 11.
    D. Wall, “Limits of Instruction-Level Parallelism”, Proc. of the 4th Int. Conf. on Architectural Support for Programming Languages and Operating Systems, April 1991, pp. 176–188Google Scholar
  12. 12.
    Yang, Chia. “A Multi Context Uniprocessor: Another Multithreaded Architecture.” Thesis California Polytechnic State University, San Luis Obispo, CA 1997.Google Scholar

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • Joy Shetler
  • Brian Hemme
  • Chia Yang
  • Christopher Hinsz

There are no affiliations available

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