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Virtual parallelism allows relaxing the synchronization constraints of SIMD computing paradigm

  • M. Migliardi
  • P. Baglietto
  • Massimo Maresca
3. Computer Science
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1401)

Abstract

In this paper we propose to introduce execution autonomy in the SIMD paradigm to overcome its rigidity while preserving the advantages of its synchronous programming model and we show that Virtual Parallelism support is a necessary condition to the profitable application of execution autonomy. We define execution autonomy as the capability of each processing element of a massively parallel computer to execute the instructions in a block of code of a single common program autonomously and asynchronously. We define virtual parallelism as the capability to emulate a n processors array on a m processor array with n/m performance degradation. In past related works the relaxation of SIMD synchronization has been already proposed, nevertheless its relation with Virtual Parallelism has never been studied.

Keywords

Processing Element Basic Block Central Controller Processor Array Virtual Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    W. D. Hillis and G. L. Steele Jr., Data-parallel Algorithms, Communications of the ACM, Vol. 29, No. 12, pp. 1170–1183, Dec. 1986.Google Scholar
  2. 2.
    M. Maresca, M. A. Lavin and H. Li, Parallel Architectures for Vision, Proceedings of the IEEE, Vol. 76, No. 8, August 1988.Google Scholar
  3. 3.
    M. Maresca, Polymorphic Processor Array, IEEE Trans. on Parallel and Distributed Systems, Vol. 4, No. 5, pp. 490–506, May 1993Google Scholar
  4. 4.
    R. Miller, V. K. Prasanna-Kumar, D. Reissis e Q. F. Stout, Parallel Computations on Reconfigurable Meshes, IEEE Trans. on Computers Vol. 42, No. 6, giugno 1993, pp. 678–692.Google Scholar
  5. 5.
    M. A. Nichols, H. J. Siegel and H. G. Dietz, Data Management and Control Flow Aspects of an SIMD/SPMD Parallel Language/Compiler, IEEE Trans. on Parallel and Distributed Systems, Vol. 4, No. 2, pp. 222–234, February 1993.Google Scholar
  6. 6.
    W. D. Hillis and L. W. Tucker, The CM-5 Connection Machine: a Scalable Supercomputer, Communications of the ACM, Vol. 36 No. 11, pp. 31–40, Nov. 1993Google Scholar
  7. 7.
    P. Baglietto, M. Maresca, M. Migliardi, Introducing Execution Autonomy in the SIMD Computing Paradigm, Proc. of the International Conference on Massively Parallel Processing Applications and Development, Delft (The Netherlands), June 21–23, 1994.Google Scholar
  8. 8.
    S. Rehfuss and D. Hammerstromm, Comparing SFMD and SPMD Computation for On-chip Multiprocessing of Intermediate Level Image Understanding Algorithms, Proc. of the Fourth IEEE International Workshop on Computer Architecture for Machine Perception, Cambridge, Massachusetts, October 20–22, 1997.Google Scholar
  9. 9.
    C. Weems, Asynchronous SIMD: An Architectural Concept for High Performance Image Processing, Proc. of the Fourth IEEE International Workshop on Computer Architecture for Machine Perception, Cambridge, Massachusetts, October 20–22, 1997.Google Scholar
  10. 10.
    M. Sato, Y. Kodama, S. Sakai, Y. Yamaguchi and Y. Koumura, Thread-Based Programming for the EM-4 Hybrid Datafow Machine, Proc. of ISCA92, pp 145–155, 1992.Google Scholar
  11. 11.
    Y. Ben-Asher, D. Gordon and A. Schuster, Optimal Simulations in Reconfigurable Processor Arrays, Technion ITT technical report, Haifa (Israel), 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • M. Migliardi
    • 1
  • P. Baglietto
    • 1
  • Massimo Maresca
    • 2
  1. 1.DIST - University of GenoaGenoaItaly
  2. 2.DEI - University of PadovaPadovaItaly

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