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VIS

  • Robert K. Brayton
  • Gary D. Hachtel
  • Alberto Sangiovanni-Vincentelli
  • Fabio Somenzi
  • Adnan Aziz
  • Szu-Tsung Cheng
  • Stephen A. Edwards
  • Sunil P. Khatri
  • Yuji Kukimoto
  • Abelardo Pardo
  • Shaz Qadeer
  • Rajeev K. Ranjan
  • Shaker Sarwary
  • Thomas R. Shiple
  • Gitanjali Swamy
  • Tiziano Villa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1166)

Keywords

Model Check Formal Verification Reachable State Fairness Constraint Error Trace 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Kenneth L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.Google Scholar
  2. 2.
    R. K. Brayton et al. HSIS: A BDD based system for formal verification. Proc. of Design Automation Conference, 1994.Google Scholar
  3. 3.
    S.-T. Cheng. Compiling Verilog into automata. Tech. Rep. UCB/ERL M94/37, May 1994.Google Scholar
  4. 4.
    E.M. Sentovich et al. SIS: a system for sequential circuit synthesis. Tech. Rep. M92/41, May 1992.Google Scholar
  5. 5.
    VIS Home Page: http://www-cad.eecs.berkeley.edu/∼visGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Robert K. Brayton
    • 1
  • Gary D. Hachtel
    • 2
  • Alberto Sangiovanni-Vincentelli
    • 1
  • Fabio Somenzi
    • 2
  • Adnan Aziz
    • 3
  • Szu-Tsung Cheng
    • 1
  • Stephen A. Edwards
    • 1
  • Sunil P. Khatri
    • 1
  • Yuji Kukimoto
    • 1
  • Abelardo Pardo
    • 2
  • Shaz Qadeer
    • 1
  • Rajeev K. Ranjan
    • 1
  • Shaker Sarwary
    • 4
  • Thomas R. Shiple
    • 1
  • Gitanjali Swamy
    • 1
  • Tiziano Villa
    • 1
  1. 1.Department of EECSUniversity of CaliforniaBerkeley
  2. 2.Department of ECEUniversity of ColoradoBoulder
  3. 3.Department of ECEUniversity of Texas at Austin
  4. 4.Lattice SemiconductorMilpitas

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