Part of the Lecture Notes in Computer Science book series (LNCS, volume 1166)
KeywordsModel Check Formal Verification Reachable State Fairness Constraint Error Trace
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- 1.Kenneth L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.Google Scholar
- 2.R. K. Brayton et al. HSIS: A BDD based system for formal verification. Proc. of Design Automation Conference, 1994.Google Scholar
- 3.S.-T. Cheng. Compiling Verilog into automata. Tech. Rep. UCB/ERL M94/37, May 1994.Google Scholar
- 4.E.M. Sentovich et al. SIS: a system for sequential circuit synthesis. Tech. Rep. M92/41, May 1992.Google Scholar
- 5.VIS Home Page: http://www-cad.eecs.berkeley.edu/∼visGoogle Scholar
© Springer-Verlag Berlin Heidelberg 1996