Deterministic simulation of idealized parallel computers on more realistic ones

  • H. Alt
  • T. Hagerup
  • K. Mehlhorn
  • F. P. Preparata
Communications
First Online:
Part of the Lecture Notes in Computer Science book series (LNCS, volume 233)

Abstract

We describe a deterministic simulation of PRAMs on module parallel computers (MPCs) and on processor networks of bounded degree. The simulating machines have the same number n of processors as the simulated PRAM, and if the size of the PRAM's shared memory is polynomial in n, each PRAM step is simulated by O(log n) MPC steps or by O((log n)2) steps of the bounded degree network. This improves upon a previous result by Upfal and Wigderson. We also prove an Ω((log n)2/log log n) lower bound on the number of steps needed to simulate one PRAM step on a bounded degree network under the assumption that the communication in the network is point-to-point.

Keywords

Shared Memory Time Stamp Memory Module Deterministic Simulation Network Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • H. Alt
    • 1
  • T. Hagerup
    • 2
  • K. Mehlhorn
    • 3
  • F. P. Preparata
    • 3
  1. 1.Fachbereich MathematikFreie Universität BerlinBerlin 33FRG
  2. 2.Fachbereich 10, InformatikUniversität des SaarlandesSaarbrückenFRG
  3. 3.Coordinated Science LaboratoryUniversity of IllinoisUrbanaUSA

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