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State clock logic: A decidable real-time logic

  • Jean-François Raskin
  • Pierre-Yves Schobbens
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1201)

Abstract

In this paper we define a real-time logic called SC logic. This logic is defined in the framework of State Clock automata, the state variant of the Event Clock automata of Alur et al [6]. Unlike timed automata [4], they are complementable and thus language inclusion becomes decidable. SC automata and SC logic are less expressive than timed automata and MITL but seem expressive enough in practice. A procedure to translate each SC formula into a SC automaton is presented. The main contribution of this paper is to complete the framework of this class of determinizable automata with a temporal logic and to introduce the notion of event clock in the domain of temporal logic.

Keywords

Model Check Temporal Logic Linear Temporal Logic Satisfiability Problem State Clock 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Jean-François Raskin
    • 1
  • Pierre-Yves Schobbens
    • 1
  1. 1.Computer Science InstituteUniversity of NamurNamurBelgium

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